Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLXP (32-bit)

Test 1: uops

Code:

  stlxp w0, w1, w2, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	3309	1019	1	1018	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3054	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3040	1001	1	1000	1000	51855	1000	1000	3000	1	1000

Test 2: throughput

Code:

  stlxp w0, w1, w2, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.1324

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20209	32031	20321	10231	10090	10230	10003	35473	351109	20106	10203	10003	10203	30012	10002	10000	10100
20204	31354	20103	10103	10000	10102	10002	35491	350708	20104	10202	10002	10202	30006	10003	10000	10100
20204	31358	20103	10103	10000	10102	10002	35491	351180	20104	10202	10002	10202	30006	10003	10000	10100
20204	31293	20103	10103	10000	10102	10002	35491	351120	20104	10202	10002	10202	30006	10003	10000	10100
20204	31350	20103	10103	10000	10102	10033	35828	354368	20166	10233	10033	10202	30006	10003	10000	10100
20204	31344	20103	10103	10000	10102	10002	35491	351266	20104	10202	10002	10202	30006	10003	10000	10100
20204	31355	20103	10103	10000	10102	10002	35491	351173	20104	10202	10002	10202	30006	10003	10000	10100
20204	31352	20103	10103	10000	10102	10002	35491	351290	20104	10202	10002	10202	30006	10003	10000	10100
20204	31344	20103	10103	10000	10102	10002	35491	351144	20104	10202	10002	10202	30006	10003	10000	10100
20204	31336	20103	10103	10000	10102	10002	35491	351070	20104	10202	10002	10202	30006	10003	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.1426

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20029	32007	20228	10138	10090	10137	10002	35244	352476	20014	10022	10002	10020	30000	10001	10000	10010
20024	31412	20011	10011	10000	10010	10000	35235	352285	20010	10020	10000	10020	30000	10001	10000	10010
20024	31429	20011	10011	10000	10010	10000	35235	352363	20010	10020	10000	10054	30093	10034	10000	10010
20024	31432	20011	10011	10000	10010	10000	35235	352268	20010	10020	10000	10020	30000	10001	10000	10010
20024	31428	20011	10011	10000	10010	10000	35235	352360	20010	10020	10000	10020	30000	10001	10000	10010
20024	31424	20011	10011	10000	10010	10000	35235	352259	20010	10020	10000	10020	30000	10001	10000	10010
20024	31430	20011	10011	10000	10010	10000	35235	352234	20010	10020	10000	10020	30000	10001	10000	10010
20024	31424	20011	10011	10000	10010	10000	35235	352453	20010	10020	10000	10020	30000	10001	10000	10010
20024	31428	20011	10011	10000	10010	10000	35235	352311	20010	10020	10000	10020	30000	10001	10000	10010
20024	31433	20011	10011	10000	10010	10000	35235	352499	20010	10020	10000	10020	30000	10001	10000	10010

Test 3: throughput

Code:

  stlxp w0, w1, w2, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	30156	10119	101	10018	100	10000	300	528893	10100	200	10004	200	30012	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528767	10100	200	10004	200	30012	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100
10204	30049	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100
10204	30051	10101	101	10000	100	10000	300	529001	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	30165	10029	11	10018	10	10000	30	528855	10010	20	10004	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10036	30	529179	10046	20	10048	20	30000	1	10000	10
10024	30096	10011	11	10000	10	10000	30	528981	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10036	30	529179	10046	20	10048	20	30000	1	10000	10