Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSB (register, sxtw, 32-bit)

Test 1: uops

Code:

  ldrsb w0, [x6, w7, sxtw]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056531027110261000823810001000200011000
10045541001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000
10045471001110001000811210001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570151401083010710001301301000318595396938964010630210100046022420008300031000030100
4020470053401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020570079401113010910002301351000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570288400183001710001300401000018597066947344001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101001518620956949534006030067100176002020000300021000030010
4002470046400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101001518598816947764006030067100176002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018615966955114001030020100006002020000300021000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570304401083010710001301301000318597016939624010630210100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020570084401143011210002301371000318604726944264010630212100046022420008300031000030100
4020470047401033010310000301031000318596086940744010630212100046022420008300031000030100
4020470048401033010310000301031000318596356940854010630212100046022420008300031000030100
4020470047401033010310000301031001518599266941424015030247100176022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570161400183001710001300401000018596046936544001030020100006011420034300081000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470051400133001310000300101000018596256947104001030020100006002020000300021000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470047400133001310000300101000018594636946444001030020100006009820026300081000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010

Test 4: throughput

Count: 8

Code:

  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205401678012510180024100800083002802628010820080012200160024180000100
80204400648010510180004100800083006401428010820080012200160024180000100
80204400508010110180000100800083006401428010820080012200160024180000100
80204400498010110180000100800083006401428010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80205403458013110180030100800103006402088011020080014200160024180000100
80204400458010110180000100800593006449148015920080072200160024180000100
80204400468010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402578004511800341080010304001428002020800142016000018000010
80024400588001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400618001111800001080000306405628001020800002016000018000010