Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, 32-bit)

Test 1: uops

Code:

  ldr w0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	950	1001	1	1000	1000	12324	1000	1000	1	1000
1004	765	1001	1	1000	1000	12169	1000	1000	1	1000
1004	753	1001	1	1000	1000	11901	1000	1000	1	1000
1004	743	1001	1	1000	1000	11494	1000	1000	1	1000
1004	758	1001	1	1000	1000	11973	1000	1000	1	1000
1004	759	1001	1	1000	1000	11530	1000	1000	1	1000
1004	747	1001	1	1000	1000	11557	1000	1000	1	1000
1004	756	1001	1	1000	1000	11746	1000	1000	1	1000
1004	756	1001	1	1000	1000	11611	1000	1000	1	1000
1004	743	1001	1	1000	1000	11980	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5021

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40430	80105	101	80004	100	80010	300	255517	80110	200	80014	200	1	80000	100
80204	40176	80101	101	80000	100	80010	300	485807	80110	200	80014	200	1	80000	100
80204	40145	80101	101	80000	100	80008	300	642158	80108	200	80012	200	1	80000	100
80204	40163	80101	101	80000	100	80008	300	642104	80108	200	80012	200	1	80000	100
80204	40166	80101	101	80000	100	80008	300	642176	80108	200	80012	200	1	80000	100
80205	40197	80138	101	80037	100	80009	300	642857	80109	200	80012	200	1	80000	100
80204	40459	80101	101	80000	100	80057	300	568977	80157	200	80070	200	1	80000	100
80204	40171	80101	101	80000	100	80009	300	642317	80109	200	80012	200	1	80000	100
80204	40163	80101	101	80000	100	80009	300	642227	80109	200	80012	200	1	80000	100
80204	40156	80101	101	80000	100	80009	300	642281	80109	200	80012	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5162

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	43557	80015	11	80004	10	80010	30	380884	80020	20	80014	20	1	80000	10
80024	41323	80011	11	80000	10	80000	30	660849	80010	20	80000	20	1	80000	10
80024	41346	80011	11	80000	10	80000	30	661739	80010	20	80000	20	1	80000	10
80024	41276	80011	11	80000	10	80000	30	661929	80010	20	80000	20	1	80000	10
80024	41294	80011	11	80000	10	80000	30	661697	80010	20	80000	20	1	80000	10
80024	41295	80011	11	80000	10	80000	30	661856	80010	20	80000	20	1	80000	10
80024	41291	80011	11	80000	10	80000	30	662336	80010	20	80000	20	1	80000	10
80025	41460	80043	11	80032	10	80000	30	661706	80010	20	80000	20	1	80000	10
80024	41285	80011	11	80000	10	80000	30	661511	80010	20	80000	20	1	80000	10
80024	41291	80011	11	80000	10	80000	30	662052	80010	20	80000	20	1	80000	10