Icestorm: CCMN (immediate, 32-bit) measurements

Code:

  ccmn w1, #3, #0, hi

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  ccmn w1, #3, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519112	20108	20216	30218	20001	10100
20204	20030	20101	20101	20107	519413	20107	20214	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20205	20061	20117	20117	20149	519548	20108	20216	30221	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519507	20017	20032	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 2->2

Code:

  ccmn w0, #3, #0, hi

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10209	254770	10208	10208	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254734	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	256291	10323	10323	20216	10101	100
10204	10030	10201	10201	10208	254357	10210	10212	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255236	10029	10032	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63249	160116	160116	160120	687346	160155	160257	160222	160015	100
160204	63164	160117	160117	160121	688456	160124	160226	160220	160012	100
160204	63134	160115	160115	160120	689052	160124	160226	160220	160015	100
160204	63093	160111	160111	160118	689181	160120	160220	160216	160010	100
160204	63103	160111	160111	160115	689796	160118	160220	160220	160012	100
160204	63117	160112	160112	160118	689226	160118	160220	160220	160014	100
160204	63174	160113	160113	160118	689288	160118	160220	160224	160014	100
160204	63119	160112	160112	160118	686358	160118	160220	160220	160012	100
160204	63081	160114	160114	160120	687369	160120	160220	160260	160048	100
160204	63117	160112	160112	160118	688910	160118	160220	160216	160012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7882

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64562	160026	160026	0	160030	698028	160030	160040	160020	160001	10
160024	63343	160011	160011	0	160010	700311	160010	160020	160020	160001	10
160024	63086	160011	160011	0	160010	701725	160010	160020	160020	160001	10
160024	63084	160011	160011	0	160010	700971	160010	160020	160020	160001	10
160024	63030	160011	160011	0	160010	696956	160010	160020	160020	160001	10
160024	63031	160011	160011	0	160010	700137	160010	160020	160020	160001	10
160024	63059	160011	160011	0	160010	698966	160010	160020	160020	160001	10
160024	63018	160011	160011	0	160010	697650	160010	160020	160020	160001	10
160024	63089	160011	160011	0	160010	701841	160010	160020	160020	160001	10
160024	63046	160011	160011	0	160010	694602	160010	160020	160020	160001	10

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24017	50103	40101	10002	40109	10003	315226	40012	50112	40209	10003	80224	20008	40002	100
50204	24006	50104	40101	10003	40112	10004	315063	40013	50112	40209	10003	80232	20008	40005	100
50204	23991	50103	40101	10002	40112	10004	314875	40013	50112	40209	10003	80218	20006	40003	100
50204	23999	50105	40102	10003	40112	10004	315129	40018	50116	40212	10004	80232	20008	40005	100
50204	23991	50104	40101	10003	40112	10004	315987	40017	50116	40212	10004	80218	20006	40001	100
50204	23988	50103	40101	10002	40109	10003	315395	40018	50116	40212	10004	80224	20008	40001	100
50204	23992	50106	40103	10003	40109	10003	315411	40017	50119	40216	10004	80224	20008	40001	100
50204	23999	50105	40102	10003	40112	10004	315011	40012	50112	40209	10003	80218	20006	40001	100
50204	23990	50104	40101	10003	40112	10004	315407	40012	50112	40209	10003	80218	20006	40001	100
50204	24001	50105	40102	10003	40109	10003	315283	40012	50112	40209	10003	80218	20006	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24098	50018	40015	10003	40021	10003	0	315750	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23989	50011	40011	10000	40010	10000	0	317808	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	24012	50011	40011	10000	40010	10000	0	315510	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23956	50011	40011	10000	40010	10000	0	316523	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	24021	50011	40011	10000	40010	10000	0	315542	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	24042	50011	40011	10000	40010	10000	0	315547	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	0	315510	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23977	50011	40011	10000	40010	10000	0	316748	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23985	50011	40011	10000	40010	10000	0	316653	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23962	50011	40011	10000	40010	10000	0	315455	0	40000	50010	40020	0	10000	80048	20008	40006	10

Test 6: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39010	80109	80109	80114	551096	80116	80216	140228	80005	100
80204	38986	80107	80107	80114	548919	80111	80212	140230	80007	100
80204	38930	80109	80109	80117	549785	80116	80216	140228	80005	100
80204	38952	80108	80108	80116	547003	80108	80208	140228	80003	100
80204	38944	80106	80106	80116	549899	80111	80212	140228	80005	100
80204	39012	80106	80106	80116	550182	80111	80212	140220	80004	100
80204	38969	80103	80103	80114	549972	80116	80216	140228	80005	100
80204	39005	80105	80105	80114	550481	80111	80212	140228	80005	100
80204	38944	80107	80107	80116	549785	80116	80216	140220	80003	100
80204	38969	80103	80103	80114	550183	80116	80216	140228	80007	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5561

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39163	80034	80034	80046	0	549052	0	80042	80044	0	140020	80011	10
80024	38912	80021	80021	80020	0	549076	0	80020	80020	0	140020	80011	10
80024	38917	80021	80021	80020	0	550581	0	80020	80020	0	140020	80011	10
80024	38946	80021	80021	80020	0	549916	0	80020	80020	0	140020	80011	10
80025	38918	80053	80053	80076	0	550642	0	80020	80020	0	140020	80011	10
80024	38859	80021	80021	80020	0	550042	0	80020	80020	0	140020	80011	10
80024	38970	80021	80021	80020	0	550642	0	80020	80020	0	140020	80011	10
80024	38913	80021	80021	80020	0	548666	0	80020	80020	0	140020	80011	10
80024	38969	80021	80021	80020	0	550341	0	80020	80020	0	140020	80011	10
80024	38894	80021	80021	80020	0	550341	0	80020	80020	0	140020	80011	10

CCMN (immediate, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations