Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DMB (LD)

Test 1: uops

Code:

  dmb ld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)? int output thing (e9)? ldst retires (ed)
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000
10044040100111000100040001000100011000

Test 2: throughput

Code:

  dmb ld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1020440042101051011000410010006300400241010620010006200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010012300400481011220010012200110000100
1020440040101051011000410010004300400161010420010004200110000100
1020440040101051011000410010004300400161010420010004200110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1002440040100151110004101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101001230400481002220100122011000010
1002440040100111110000101000030400001001020100002011000010
1002440040100111110000101000030400001001020100002011000010