Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NEG (register, asr, 64-bit)

Test 1: uops

Code:

  neg x0, x0, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000

Test 2: Latency 1->2

Code:

  neg x0, x0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045291001010410210102102000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10205200602011520115101375291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010

Test 3: throughput

Count: 8

Code:

  neg x0, x8, asr #17
  neg x1, x8, asr #17
  neg x2, x8, asr #17
  neg x3, x8, asr #17
  neg x4, x8, asr #17
  neg x5, x8, asr #17
  neg x6, x8, asr #17
  neg x7, x8, asr #17
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802045361116037716037708033401360838008013080234008023616001680100
802045340416011716011708013001360838008013080236008023616001780100
802045340416011716011708013001360838008013080236008023616001780100
802045340416011716011708013001360838008013080236008029016008380100
802045340416011716011708013001360838008013080236008023616001780100
802045340416011716011708013001360838008013080236008023616001780100
802045340416011716011708013001360838008013080236008044516027680100
802055348616022516022508022901360801008013080234008023616001780100
81452574961615291610125178099901360557008013180238008023616001780100
802045345616018316018308018301360838008013080236008023616001780100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8002453414160039160039800511360530800968010880020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201359903800208002080020001600110080010
8002453371160021160021800201360856801438016080058001600290080010