Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
swpah w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 72005 | 34371 | 2005 | 1 | 2004 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34118 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34144 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34861 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34450 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 35195 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34110 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34187 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34285 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34270 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
Code:
swpah w0, w1, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0019
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30207 | 60584 | 30185 | 10128 | 0 | 20057 | 10131 | 0 | 20004 | 35254 | 125434 | 30106 | 10202 | 20004 | 10202 | 40008 | 10001 | 20000 | 10100 |
| 16606 | 33162 | 16564 | 5558 | 0 | 11006 | 5560 | 0 | 20004 | 35252 | 125493 | 30106 | 10202 | 20004 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60028 | 30103 | 10101 | 0 | 20002 | 10102 | 0 | 20016 | 35285 | 126001 | 30123 | 10207 | 20017 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 14228 | 23084 | 11683 | 7057 | 0 | 4626 | 6613 | 0 | 20004 | 35251 | 125435 | 30106 | 10202 | 20004 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30205 | 60026 | 30115 | 10105 | 0 | 20010 | 10106 | 0 | 20002 | 35250 | 125492 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35250 | 125484 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 125498 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 125515 | 30103 | 10201 | 20003 | 10206 | 40025 | 10006 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 125470 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35250 | 125543 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
Result (median cycles for code): 6.0015
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30026 | 60282 | 30060 | 10027 | 20033 | 10027 | 20002 | 35069 | 125636 | 30013 | 10021 | 20003 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60022 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125597 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125569 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125563 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125553 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125522 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125541 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125516 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125527 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 125524 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
Code:
swpah w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 22.0044
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20207 | 220313 | 20170 | 103 | 20067 | 102 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20205 | 220082 | 20127 | 101 | 20026 | 100 | 20004 | 300 | 2175590 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20205 | 220071 | 20125 | 101 | 20024 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20205 | 220118 | 20125 | 101 | 20024 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175638 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175646 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175646 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
Result (median cycles for code): 22.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20025 | 220378 | 20035 | 11 | 20024 | 10 | 20004 | 30 | 2172819 | 20014 | 20 | 20004 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20024 | 30 | 2173267 | 20034 | 20 | 20024 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20025 | 220073 | 20035 | 11 | 20024 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40052 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40048 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |