Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLRB

Test 1: uops

Code:

  stlrb w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	6156	1019	1	1018	1000	104730	1000	1000	2000	1	1000
1004	6065	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6065	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000
1004	6058	1001	1	1000	1000	104588	1000	1000	2000	1	1000

Test 2: throughput

Count: 8

Code:

  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]
  stlrb w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 6.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	480151	80119	101	80018	100	80000	300	8557552	80100	200	80004	200	160194	1	80000	100
80205	480096	80119	101	80018	100	80000	300	8557552	80100	200	80004	200	160008	1	80000	100
80204	480056	80101	101	80000	100	80036	300	8557876	80136	200	80052	200	160008	1	80000	100
80204	480056	80101	101	80000	100	80000	300	8557552	80100	200	80004	202	160100	2	80000	100
80204	480056	80101	101	80000	100	80000	300	8557552	80100	200	80004	200	160008	1	80000	100
80205	480096	80119	101	80018	100	80000	300	8557552	80100	200	80004	200	160008	1	80000	100
80204	480056	80101	101	80000	100	80036	300	8557876	80136	200	80052	200	160008	1	80000	100
80204	480056	80101	101	80000	100	80000	300	8557552	80100	200	80004	200	160104	1	80000	100
80204	480056	80101	101	80000	100	80000	300	8557552	80100	200	80004	200	160008	1	80000	100
80205	480096	80119	101	80018	100	80000	300	8557552	80100	200	80004	200	160104	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 6.0008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80026	480197	80047	11	80036	10	80036	30	8558160	80046	20	80052	20	160100	1	80000	10
80024	480063	80011	11	80000	10	80000	30	8557694	80010	20	80004	20	160008	1	80000	10
80025	480103	80029	11	80018	10	80000	30	8557694	80010	20	80000	20	160000	1	80000	10
80025	480121	80029	11	80018	10	80036	30	8558018	80046	20	80051	20	160000	1	80000	10
80024	480063	80011	11	80000	10	80000	30	8557694	80010	20	80000	20	160104	1	80000	10
80024	480063	80011	11	80000	10	80000	30	8557694	80010	20	80000	20	160000	1	80000	10
80025	480103	80029	11	80018	10	80000	30	8557694	80010	20	80000	20	160000	1	80000	10
80024	480063	80011	11	80000	10	80036	30	8558018	80046	20	80045	20	160000	1	80000	10
80024	480063	80011	11	80000	10	80000	30	8557694	80010	20	80000	20	160102	1	80000	10
80024	480063	80011	11	80000	10	80000	30	8557694	80010	20	80000	20	160000	1	80000	10