Icestorm: TBNZ (taken) measurements

Code:

  tbnz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	4942	3326	3326	4342	11613	3871	4452	1148	1
1004	631	1009	1009	1012	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1

Count: 8

Code:

  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4

Initialization

  mov x0, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0615

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	94506	83586	83586	0	0	85078	0	240318	80106	80206	80206	1	100
80204	84728	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100
80204	85044	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100
80204	84934	80105	80105	0	0	80106	0	240318	80106	80206	80268	1	100
80204	85011	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100
80204	84925	80105	80105	0	0	80106	0	254043	84681	85361	80206	1	100
80204	85171	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100
80204	84895	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100
80204	84906	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100
80204	84918	80105	80105	0	0	80106	0	240318	80106	80206	80206	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.9560

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	359458	109545	109545	120420	240141	80047	80057	80021	1	10
80024	317809	80012	80012	80011	240033	80011	80021	80039	1	10
80024	316601	80012	80012	80011	240033	80011	80021	80021	1	10
80024	317101	80012	80012	80011	240124	80042	80052	80021	1	10
80024	317105	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316688	80012	80012	80011	240080	80027	80037	80021	1	10
80024	316689	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316603	80012	80012	80011	240105	80036	80046	80024	1	10
80025	316617	80024	80024	80026	240033	80011	80021	80021	1	10
80024	316414	80012	80012	80011	240050	80017	80027	80021	1	10

TBNZ (taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations