Icestorm: NGCS (register, 64-bit) measurements

Code:

  ngcs x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  ngcs x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	0	251562	0	10109	10210	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20296	10015	10100
10204	10030	10101	10101	10108	0	251819	0	10107	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100
10204	10030	10101	10101	10108	0	251774	0	10108	10208	0	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253256	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20118	10025	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253519	10066	10068	20020	10011	10010

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngcs x0, x1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20208	508824	20211	20212	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20206	20090	20231	20231	20284	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20028	509965	20031	20032	30020	20011	10010
20024	20030	20021	20021	20020	510364	20066	20068	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	30020	20011	10010

Test 4: Latency 3->2

Chain cycles: 1

Code:

  ngcs x0, x1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519548	20108	20214	30224	20001	20100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	20100
20205	20060	20115	20115	20147	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30221	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519495	20018	20036	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 5: Latency 3->3

Code:

  ngcs x0, x1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10033	10201	10201	10212	253344	10210	10212	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	0	253427	0	0	10029	10032	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	253383	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	10020	0	252876	0	0	10030	10032	0	0	20044	10011	10010

Test 6: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ngcs x0, x8
  ands xzr, xzr, xzr
  ngcs x1, x8
  ands xzr, xzr, xzr
  ngcs x2, x8
  ands xzr, xzr, xzr
  ngcs x3, x8
  ands xzr, xzr, xzr
  ngcs x4, x8
  ands xzr, xzr, xzr
  ngcs x5, x8
  ands xzr, xzr, xzr
  ngcs x6, x8
  ands xzr, xzr, xzr
  ngcs x7, x8

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7991

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	64059	160112	160112	160116	681833	160120	160222	160218	160013	80100
160204	63934	160113	160113	160118	653795	160119	160221	160216	160011	80100
160204	63933	160111	160111	160115	682061	160115	160216	160220	160015	80100
160204	63939	160111	160111	160115	682512	160118	160220	160216	160010	80100
160204	63915	160112	160112	160118	682253	160118	160220	160220	160015	80100
160204	63912	160113	160113	160119	682162	160115	160216	160256	160048	80100
160204	63935	160115	160115	160119	682224	160115	160216	160220	160015	80100
160204	63936	160111	160111	160116	682166	160119	160220	160216	160011	80100
160204	63937	160111	160111	160115	682137	160115	160216	160216	160011	80100
160204	63921	160112	160112	160116	682170	160119	160220	160216	160010	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7929

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64838	160024	160024	0	0	160028	0	644784	160010	160020	160020	160001	80010
160024	63814	160011	160011	0	0	160010	0	656683	160010	160020	160020	160001	80010
160024	63343	160011	160011	0	0	160010	0	648722	160010	160020	160020	160001	80010
160024	63409	160011	160011	0	0	160010	0	649005	160010	160020	160020	160001	80010
160024	63650	160011	160011	0	0	160010	0	656376	160010	160020	160020	160001	80010
160024	63359	160011	160011	0	0	160010	0	647471	160010	160020	160020	160001	80010
160024	63347	160011	160011	0	0	160010	0	654943	160010	160020	160020	160001	80010
160024	63359	160011	160011	0	0	160010	0	644298	160010	160020	160020	160001	80010
160024	63414	160011	160011	0	0	160010	0	643269	160010	160020	160020	160001	80010
160024	63369	160011	160011	0	0	160010	0	648623	160010	160020	160020	160001	80010

Test 7: throughput

Count: 4

Code:

  fcmp s0, s0
  ngcs x0, x4
  ngcs x1, x4
  ngcs x2, x4
  ngcs x3, x4

Initialization

  mov x4, 5
  mov x5, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6208

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24792	50108	40104	10004	40116	10005	309321	40013	50114	40211	10003	80226	20008	40002	40100
50204	24787	50108	40104	10004	40116	10005	309308	40013	50114	40211	10003	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80288	20024	40034	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309521	40041	50152	40242	10010	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6197

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24858	50016	40014	10002	40024	10004	311152	40017	50028	40034	10004	80020	20000	40001	40010
50024	24686	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	80020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	80020	20000	40001	40010

Test 8: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ngcs x0, x7
  ngcs x1, x7
  ngcs x2, x7
  ngcs x3, x7
  ngcs x4, x7
  ngcs x5, x7
  ngcs x6, x7

Initialization

  mov x7, 8
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5844

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40920	80110	80110	80119	540514	80115	80216	140234	80010	70100
80204	40922	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	540465	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	140220	80007	70100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	40937	80015	80015	80027	545743	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543052	80010	80020	140020	0	0	80001	0	0	70010
80024	40862	80011	80011	80010	543747	80061	80071	140020	0	0	80001	0	0	70010

NGCS (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations