Icestorm: LDUR (32-bit) measurements

Code:

  ldur w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	657	1027	1	1026	1000	8112	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldur w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70166	40108	30107	10001	30130	10003	1863037	695390	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60302	10017	30008	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859500	694033	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859446	694015	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40205	70162	40110	30108	10002	30135	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70154	40018	30017	10001	30040	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70053	40013	30013	10000	30010	10015	1860043	694745	40060	30067	10017	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10015	1862338	695056	40060	30067	10017	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40181	80131	101	80030	100	80008	300	336136	80108	200	80012	200	80072	1	80000	100
80204	40066	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640790	80108	200	80012	200	80072	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640232	80108	200	80012	200	80012	1	80000	100
80204	40331	80161	101	80060	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40453	80041	11	80030	10	80107	30	556468	80117	20	80129	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640256	80010	20	80000	20	80000	1	80000	10
80024	40389	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40053	80011	11	80000	10	80000	30	640310	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10

LDUR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations