Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDUR (32-bit)

Test 1: uops

Code:

  ldur w0, [x6, #1]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056571027110261000811210001000100011000
10045541001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000
10045471001110001000811210001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldur w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570166401083010710001301301000318630376953904010630212100046022410004300021000030100
4020470040401023010210000301031000318593926939934010630212100046030210017300081000030100
4020470040401023010210000301031000318595006940334010630212100046022410004300021000030100
4020470040401023010210000301031000318594466940154010630212100046022410004300021000030100
4020470040401023010210000301031000318593926939934010630212100046022410004300021000030100
4020470040401023010210000301031000318593926939934010630212100046022410004300021000030100
4020470040401023010210000301031000318593926939934010630212100046022410004300021000030100
4020570162401103010810002301351000318593926939934010630212100046022410004300021000030100
4020470040401023010210000301031000318593926939934010630212100046022410004300021000030100
4020470040401023010210000301031000318593926939934010630212100046022410004300021000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570154400183001710001300401000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470053400133001310000300101001518600436947454006030067100176002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101001518623386950564006030067100176002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010

Test 3: throughput

Count: 8

Code:

  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540181801311018003010080008300336136801082008001220080072180000100
8020440066801011018000010080008300640142801082008001220080012180000100
8020440054801011018000010080008300640790801082008001220080072180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440057801011018000010080008300640232801082008001220080012180000100
8020440331801611018006010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540453800411180030108010730556468801172080129208000018000010
8002440054800111180000108000030640256800102080000208000018000010
8002440389800111180000108000030640112800102080000208000018000010
8002440053800111180000108000030640310800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440050800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010