Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
swpab w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 72005 | 34549 | 2011 | 1 | 2010 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34206 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34161 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34166 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34191 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34210 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34169 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34208 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34218 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34173 | 2001 | 1 | 2000 | 2000 | 11782 | 2000 | 2000 | 4000 | 1 | 2000 |
Code:
swpab w0, w1, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0012
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30206 | 60300 | 30148 | 10116 | 20032 | 10119 | 20004 | 35236 | 125236 | 30106 | 10202 | 20004 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60018 | 30103 | 10101 | 20002 | 10102 | 20002 | 35233 | 125208 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35233 | 125227 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35233 | 125241 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35233 | 125232 | 30103 | 10201 | 20003 | 10206 | 40025 | 10006 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20010 | 35261 | 125367 | 30115 | 10205 | 20011 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30205 | 60022 | 30113 | 10105 | 20008 | 10105 | 20002 | 35233 | 125240 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30205 | 60016 | 30116 | 10106 | 20010 | 10106 | 20002 | 35233 | 125134 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35233 | 125152 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35233 | 125225 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
Result (median cycles for code): 6.0019
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30026 | 60272 | 30062 | 10027 | 20035 | 10029 | 20002 | 35069 | 125618 | 30013 | 10021 | 20003 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125567 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125570 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125584 | 30010 | 10020 | 20000 | 10025 | 40021 | 10005 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125557 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125527 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125558 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125637 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125593 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125567 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
Code:
swpab w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 22.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20205 | 220142 | 20124 | 101 | 20023 | 100 | 20004 | 300 | 2175584 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20024 | 300 | 2175772 | 20124 | 200 | 20024 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175609 | 20104 | 200 | 20004 | 200 | 40016 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175606 | 20104 | 200 | 20004 | 200 | 40048 | 1 | 20000 | 100 |
| 20204 | 220049 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175646 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175646 | 20104 | 200 | 20004 | 200 | 40048 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175694 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175646 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
Result (median cycles for code): 22.0039
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20026 | 220240 | 20057 | 11 | 20046 | 10 | 20004 | 30 | 2172819 | 20014 | 20 | 20004 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220046 | 20011 | 11 | 20000 | 10 | 20026 | 30 | 2173039 | 20036 | 20 | 20026 | 20 | 40048 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172843 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20025 | 220073 | 20035 | 11 | 20024 | 10 | 20024 | 30 | 2173014 | 20034 | 20 | 20024 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20024 | 30 | 2173054 | 20034 | 20 | 20024 | 20 | 40008 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172831 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172823 | 20010 | 20 | 20000 | 20 | 40048 | 1 | 20000 | 10 |