Icestorm: CCMN (register, 32-bit) measurements

Code:

  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmn w0, w1, #0, hi
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519320	20108	20214	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40228	20001	10100
20204	20030	20101	20101	20108	520470	20195	20307	40319	20022	10100
20204	20030	20101	20101	20108	519548	20108	20216	40417	20044	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519496	20018	20034	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmn w0, w1, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519320	20108	20214	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20205	20060	20115	20115	20147	519866	20148	20261	40228	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40505	20065	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40231	20001	10100
20204	20080	20124	20124	20153	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	520019	20152	20261	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 4: Latency 3->3

Code:

  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10209	254612	10211	10214	30242	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	255052	10029	10030	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63279	160111	160111	160116	684128	160118	160218	240239	160018	100
160204	63130	160114	160114	160120	690295	160120	160220	240233	160017	100
160204	63110	160110	160110	160116	689181	160120	160220	240230	160012	100
160205	63131	160152	160152	160159	686864	160118	160220	240284	160051	100
160204	63113	160119	160119	160124	687376	160118	160220	240227	160012	100
160204	62510	160111	160111	160116	689382	160123	160224	240230	160012	100
160204	63088	160112	160112	160118	688171	160120	160220	240230	160013	100
160204	63102	160113	160113	160118	689272	160120	160220	240296	160056	100
160204	63127	160112	160112	160118	684087	160156	160256	240233	160013	100
160204	63107	160119	160119	160124	689066	160117	160218	240230	160014	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7830

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	64425	160026	160026	160033	690544	160027	160038	240020	0	160001	0	0	10
160024	63178	160011	160011	160010	671641	160010	160020	240020	0	160001	0	0	10
160024	62541	160011	160011	160010	669241	160010	160020	240020	0	160001	0	0	10
160024	62649	160011	160011	160010	671944	160010	160020	240020	0	160001	0	0	10
160024	62551	160011	160011	160010	670516	160010	160020	240020	0	160001	0	0	10
160024	62661	160011	160011	160010	672087	160067	160077	240020	0	160001	0	0	10
160024	62545	160011	160011	160010	669769	160010	160020	240020	0	160001	0	0	10
160024	62691	160011	160011	160010	672147	160010	160020	240020	0	160001	0	0	10
160024	62540	160011	160011	160010	669717	160010	160020	240020	0	160001	0	0	10
160024	62631	160011	160011	160010	671028	160010	160020	240020	0	160001	0	0	10

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5996

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24018	50108	40105	10003	40117	10005	315002	40022	50122	40217	10005	120236	20008	40001	100
50204	23976	50105	40102	10003	40112	10004	315388	40018	50116	40212	10004	120236	20008	40001	100
50204	24000	50106	40103	10003	40109	10003	315502	40012	50112	40209	10003	120227	20006	40001	100
50204	23973	50109	40105	10004	40116	10004	315302	40013	50112	40209	10003	120236	20008	40001	100
50204	23979	50104	40101	10003	40112	10004	315423	40049	50156	40244	10012	120227	20006	40003	100
50204	23992	50104	40101	10003	40109	10003	315003	40017	50116	40212	10004	120227	20006	40001	100
50204	23979	50106	40103	10003	40109	10003	315364	40018	50116	40212	10004	120248	20008	40007	100
50204	24013	50104	40101	10003	40112	10004	315393	40013	50112	40209	10003	120236	20008	40001	100
50204	23972	50110	40107	10003	40115	10004	315063	40013	50112	40209	10003	120236	20008	40002	100
50204	23982	50105	40102	10003	40112	10004	315133	40017	50116	40212	10004	120236	20008	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24091	50018	40015	10003	40020	10003	316206	40000	50010	40020	10000	120020	20000	40001	10
50024	24011	50011	40011	10000	40010	10000	316470	40000	50010	40020	10000	120020	20000	40001	10
50024	24064	50011	40011	10000	40010	10000	316208	40000	50010	40020	10000	120020	20000	40001	10
50024	23972	50011	40011	10000	40010	10000	317188	40000	50010	40020	10000	120020	20000	40001	10
50024	23968	50011	40011	10000	40010	10000	317029	40000	50010	40020	10000	120020	20000	40001	10
50024	24013	50011	40011	10000	40010	10000	315863	40000	50010	40020	10000	120020	20000	40001	10
50024	23983	50011	40011	10000	40010	10000	316316	40000	50010	40020	10000	120020	20000	40001	10
50024	23980	50011	40011	10000	40010	10000	316366	40000	50010	40020	10000	120020	20000	40001	10
50024	24001	50011	40011	10000	40010	10000	315957	40000	50010	40020	10000	120020	20000	40001	10
50024	24030	50011	40011	10000	40010	10000	316342	40000	50010	40020	10000	120020	20000	40001	10

Test 7: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39026	80107	80107	80116	551094	80155	80255	210242	80007	100
80204	39052	80109	80109	80114	549980	80116	80216	210242	80007	100
80204	38984	80103	80103	80111	549899	80111	80212	210230	80003	100
80204	38923	80104	80104	80109	550985	80108	80208	210245	80010	100
80204	38983	80107	80107	80119	548462	80114	80216	210230	80003	100
80204	39022	80105	80105	80116	548570	80114	80216	210230	80004	100
80204	39042	80105	80105	80111	549137	80108	80208	210230	80003	100
80204	38970	80103	80103	80108	550985	80108	80208	210230	80003	100
80204	38974	80109	80109	80116	550563	80111	80212	210233	80011	100
80204	38996	80111	80111	80117	549066	80112	80214	210242	80006	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5555

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39177	80030	80030	80044	549562	80038	80038	210179	80053	10
80024	38877	80027	80027	80037	548801	80020	80020	210020	80011	10
80024	38867	80021	80021	80020	547608	80020	80020	210020	80011	10
80024	38856	80021	80021	80020	546785	80020	80020	210020	80011	10
80024	38917	80021	80021	80020	547873	80020	80020	210020	80011	10
80024	38930	80021	80021	80020	548500	80020	80020	210020	80011	10
80024	38900	80021	80021	80020	547608	80020	80020	210020	80011	10
80024	38918	80021	80021	80020	546097	80020	80020	210020	80011	10
80024	38910	80021	80021	80020	546380	80020	80020	210020	80011	10
80024	38871	80021	80021	80020	546112	80020	80020	210020	80011	10

CCMN (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations