Icestorm: LDRSB (register, 32-bit) measurements

Code:

  ldrsb w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	686	1027	1	1026	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	3000	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859350	693826	40106	30210	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10015	1859791	694130	40150	30251	10017	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60294	20034	30008	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70043	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60296	20034	30008	10000	30100
40204	70074	40104	30104	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70045	40102	30102	10000	30103	10003	1859473	694023	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70156	40018	30017	10001	30040	10003	1859434	693626	40016	30030	10004	60118	20034	30008	10000	30010
40024	70047	40013	30013	10000	30013	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1861650	695535	40010	30020	10000	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859490	694655	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10015	1859827	694785	40060	30071	10017	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859539	693896	40106	30210	10004	60220	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40205	70086	40112	30110	10002	30135	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70051	40103	30103	10000	30103	10003	1861093	694623	40106	30212	10004	60220	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70522	40018	30017	10001	30040	10003	1859725	694758	40016	30032	10004	60020	20000	30003	10000	30010
40025	70079	40021	30019	10002	30045	10000	1860171	693890	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70045	40012	30012	10000	30010	10052	1865722	697052	40194	30172	10052	60020	20000	30002	10000	30010
40024	70053	40012	30012	10000	30010	10026	1862714	695907	40102	30098	10026	60020	20000	30002	10000	30010
40024	70224	40036	30030	10006	30076	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70136	40024	30021	10003	30043	10013	1861156	694489	40056	30057	10013	60020	20000	30002	10000	30010
40024	70135	40024	30021	10003	30043	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70218	40036	30030	10006	30076	10000	1859517	694664	40010	30020	10000	60200	20060	30017	10000	30010
40024	70940	40108	30084	10024	30274	10144	1881179	718674	40518	30439	10144	60934	20320	30110	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40321	80135	101	80034	100	80008	300	256190	80108	200	80012	200	160028	1	80000	100
80204	40053	80101	101	80000	100	80010	300	244268	80110	200	80014	200	160024	1	80000	100
80204	40055	80105	101	80004	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640304	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80010	300	640154	80110	200	80014	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40214	80045	11	80034	10	80000	30	320238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640292	80010	20	80000	20	160000	1	80000	10
80024	40102	80017	11	80006	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640256	80010	20	80000	20	160000	1	80000	10

LDRSB (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations