Icestorm: CCMN (register, 64-bit) measurements

Code:

  ccmn x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmn x0, x1, #0, hi
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519415	20107	20214	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519516	20018	20034	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmn x0, x1, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519311	20107	20214	40228	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519956	20058	20080	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 4: Latency 3->3

Code:

  ccmn x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10212	254581	10211	10214	30242	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255086	10029	10030	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	63251	160112	160112	160118	686288	160122	160222	240227	0	160013	0	0	100
160204	63083	160112	160112	160117	691935	160118	160220	240236	0	160018	0	0	100
160204	63127	160115	160115	160120	686358	160118	160220	240236	0	160014	0	0	100
160204	63141	160117	160117	160123	691935	160118	160220	240230	0	160011	0	0	100
160204	63147	160113	160113	160119	687239	160115	160216	240224	0	160010	0	0	100
160204	63125	160112	160112	160118	688095	160118	160220	240230	0	160012	0	0	100
160205	62591	160148	160148	160153	692101	160118	160220	240230	0	160012	0	0	100
160204	63130	160115	160115	160120	686737	160124	160224	240230	0	160012	0	0	100
160204	63144	160115	160115	160120	690395	160120	160220	240224	0	160010	0	0	100
160204	63130	160115	160115	160120	688458	160120	160224	240230	0	160012	0	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7830

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64516	160021	160021	160026	697644	160026	160038	240020	160001	10
160024	63340	160011	160011	160010	671925	160010	160020	240020	160001	10
160024	62555	160011	160011	160010	671333	160010	160020	240020	160001	10
160024	62697	160011	160011	160010	671386	160010	160020	240020	160001	10
160024	62560	160011	160011	160010	669800	160010	160020	240020	160001	10
160024	62637	160011	160011	160010	672174	160010	160020	240020	160001	10
160024	62590	160011	160011	160010	670030	160010	160020	240020	160001	10
160024	62704	160011	160011	160010	672298	160010	160020	240020	160001	10
160024	62561	160011	160011	160010	669949	160010	160020	240020	160001	10
160025	62702	160064	160064	160072	668811	160010	160020	240020	160001	10

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5996

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24023	50105	40102	10003	40112	10004	315483	40017	50118	40214	10004	120239	20008	40002	100
50204	24101	50106	40103	10003	40113	10004	315011	40012	50112	40209	10003	120242	20008	40004	100
50204	23982	50105	40102	10003	40112	10004	315447	40012	50112	40209	10003	120227	20006	40001	100
50204	24138	50105	40103	10002	40110	10003	315132	40017	50116	40212	10004	120227	20006	40001	100
50204	23987	50104	40101	10003	40112	10004	314801	40012	50112	40209	10003	120236	20008	40002	100
50204	23979	50103	40101	10002	40109	10003	315522	40017	50116	40212	10004	120236	20008	40001	100
50204	23999	50105	40102	10003	40112	10004	315087	40017	50119	40216	10004	120227	20006	40003	100
50204	23992	50105	40102	10003	40112	10004	315619	40017	50116	40212	10004	120227	20006	40001	100
50204	23966	50104	40101	10003	40109	10003	315070	40013	50112	40209	10003	120236	20008	40001	100
50204	23994	50110	40107	10003	40115	10004	315702	40012	50112	40209	10003	120236	20008	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24127	50018	40015	10003	40020	10003	317171	40022	50032	40037	10005	120020	20000	40001	10
50024	23972	50011	40011	10000	40010	10000	316169	40000	50010	40020	10000	120020	20000	40001	10
50024	24053	50011	40011	10000	40010	10000	315708	40000	50010	40020	10000	120020	20000	40001	10
50024	24003	50011	40011	10000	40010	10000	316461	40000	50010	40020	10000	120020	20000	40001	10
50024	24038	50011	40011	10000	40010	10000	316681	40000	50010	40020	10000	120020	20000	40001	10
50024	24030	50011	40011	10000	40010	10000	315898	40000	50010	40020	10000	120020	20000	40001	10
50024	24022	50011	40011	10000	40010	10000	316333	40000	50010	40020	10000	120020	20000	40001	10
50024	23981	50011	40011	10000	40010	10000	316677	40000	50010	40020	10000	120020	20000	40001	10
50024	23974	50011	40011	10000	40010	10000	317393	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316143	40000	50010	40020	10000	120020	20000	40001	10

Test 7: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	38944	80109	80109	80113	550147	80117	80218	210236	80007	100
80204	38922	80106	80106	80112	548136	80155	80256	210242	80004	100
80204	38967	80103	80103	80111	549137	80108	80208	210242	80004	100
80204	38949	80104	80104	80108	549880	80111	80212	210230	80003	100
80204	38989	80109	80109	80116	548756	80116	80216	210242	80005	100
80204	39005	80105	80105	80114	550503	80116	80216	210230	80003	100
80204	39003	80104	80104	80111	550390	80116	80216	210242	80004	100
80204	38937	80104	80104	80114	548220	80111	80212	210242	80006	100
80204	38984	80103	80103	80108	550455	80114	80216	210221	80005	100
80204	38970	80104	80104	80114	549185	80108	80208	210230	80004	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5558

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39215	80030	80030	80039	0	549469	0	0	80039	80040	0	0	210065	80017	10
80024	38891	80028	80028	80038	0	547424	0	0	80020	80020	0	0	210020	80011	10
80024	38981	80028	80028	80038	7084	800340	158584	4385	96253	93239	8403	79	210020	80011	10
80025	38946	80058	80058	80082	0	548164	0	0	80020	80020	0	0	210020	80011	10
80024	38851	80021	80021	80020	0	546608	0	0	80020	80020	0	0	210020	80011	10
80024	38881	80021	80021	80020	0	547196	0	0	80020	80020	0	0	210185	80056	10
80024	38911	80021	80021	80020	0	544422	0	0	80020	80020	0	0	210020	80011	10
80024	38938	80021	80021	80020	0	548164	0	0	80020	80020	0	0	210020	80011	10
80024	38872	80021	80021	80020	0	548130	0	0	80079	80081	0	0	210020	80011	10
80024	38957	80021	80021	80020	0	545261	0	0	80020	80020	0	0	210020	80011	10

CCMN (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations