Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOV (from sp, 64-bit)

Test 1: uops

Code:

  mov x0, sp

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.500

Integer unit issues: 0.501

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	544	500	500	499	1497	499	1000	1000	500	1000
1004	291	500	500	499	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000
1004	280	501	501	500	1500	500	1000	1000	501	1000

Test 2: throughput

Count: 8

Code:

  mov x0, sp
  mov x1, sp
  mov x2, sp
  mov x3, sp
  mov x4, sp
  mov x5, sp
  mov x6, sp
  mov x7, sp

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	20288	40010	40010	40013	120039	40013	80226	80227	39910	80100
80204	20107	40010	40010	40013	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120039	40013	80227	80227	39910	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	80224	39909	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	21948	40021	40021	40024	120053	40011	80020	80020	40001	80010
80024	20166	40011	40011	40010	120045	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	80020	40001	80010