Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLDL2KEEP)

Test 1: uops

Code:

  prfm pldl2keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2068	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2056	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pldl2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0144

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21121	20105	10105	10000	10110	10000	61419	350875	20105	10207	10007	10207	10007	10006	10000	10100
20204	20144	20106	10106	10000	10105	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100
20204	20144	20105	10105	10000	10106	10000	61440	350939	20106	10208	10008	10208	10008	10005	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0201

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20720	20012	10012	10000	10015	10000	60977	352939	20015	10027	10007	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pldl2keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.9298

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20487	10101	101	10000	100	10006	300	357176	10106	200	10012	200	10012	1	10000	100
10204	20473	10101	101	10000	100	10000	300	355804	10100	200	10008	200	10012	1	10000	100
10204	20506	10101	101	10000	100	10000	300	357324	10100	200	10004	200	10012	1	10000	100
10204	20446	10101	101	10000	100	10000	300	342400	10100	200	10006	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10014	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.8718

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19996	10011	11	10000	10	10006	30	325212	10016	20	10012	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	19335	10011	11	10000	10	10000	30	336884	10010	20	10000	20	10000	1	10000	10