Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (SY)

Test 1: uops

Code:

  dsb sy

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	16033	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16033	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000

Test 2: throughput

Code:

  dsb sy

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	160033	10105	101	10004	100	10039	300	44388	10139	200	10039	200	1	10000	100
10204	160033	10105	101	10004	100	10004	300	40016	10104	200	10004	204	1	10000	100
10204	160509	10220	102	10118	101	10113	303	43102	10214	202	10113	204	1	10000	100
10204	160454	10228	104	10124	103	10040	300	44118	10140	200	10040	200	1	10000	100
10204	160063	10114	101	10013	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160441	10169	101	10068	100	10050	306	40976	10152	204	10050	200	1	10000	100
10204	160028	10107	101	10006	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160057	10113	101	10012	100	10148	309	43592	10251	206	10148	200	1	10000	100
10204	160586	10252	102	10150	101	10173	300	42500	10273	201	10173	202	1	9999	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	160033	10017	11	10006	10	10006	30	40024	10016	20	10006	20	0	1	10000	0	10
10024	160033	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10011	30	40044	10021	20	10011	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10004	30	40016	10014	20	10004	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	10000	10	10016	30	40064	10026	20	10016	20	0	1	10000	0	10