Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLIL3STRM)

Test 1: uops

Code:

  prfm plil3strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2135	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2155	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2155	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2146	1001	1	1000	1000	35358	1000	1000	1000	1	1000
1004	2115	1001	1	1000	1000	35606	1000	1000	1000	1	1000
1004	2117	1001	1	1000	1000	35326	1000	1000	1000	1	1000
1004	2144	1001	1	1000	1000	35638	1000	1000	1000	1	1000
1004	2128	1001	1	1000	1000	35642	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm plil3strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0176

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21254	20103	10103	10000	10102	10004	61269	351167	20113	10211	10011	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100
20204	20176	20105	10105	10000	10110	10004	61289	351173	20114	10212	10012	10212	10012	10005	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0145

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	21164	20012	10012	10000	10016	10000	61215	349043	20015	10027	10007	10020	10000	10001	10000	10010
20024	20041	20011	10011	10000	10010	10000	61201	349043	20010	10020	10000	10020	10000	10001	10000	10010
20024	20041	20011	10011	10000	10010	10000	61201	349043	20010	10020	10000	10020	10000	10001	10000	10010
20024	20041	20011	10011	10000	10010	10000	61201	349043	20010	10020	10000	10020	10000	10001	10000	10010
20024	20041	20011	10011	10000	10010	10000	61201	349043	20010	10020	10000	10020	10000	10001	10000	10010
20024	20041	20011	10011	10000	10010	10000	60467	350971	20015	10027	10008	10020	10000	10001	10000	10010
20024	20068	20011	10011	10000	10010	10000	61105	349673	20010	10020	10000	10020	10000	10001	10000	10010
20024	20068	20011	10011	10000	10010	10000	61105	349673	20010	10020	10000	10020	10000	10001	10000	10010
20024	20068	20011	10011	10000	10010	10000	61105	349673	20010	10020	10000	10020	10000	10001	10000	10010
20024	20068	20011	10011	10000	10010	10000	61105	349673	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm plil3strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20058	10101	101	10000	100	10006	300	349012	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10000	300	347338	10100	200	10008	200	10012	1	10000	100
10204	19812	10101	101	10000	100	10004	300	345536	10104	200	10012	200	10012	1	10000	100
10204	19937	10101	101	10000	100	10000	300	348582	10100	200	10004	200	10010	1	10000	100
10204	20160	10101	101	10000	100	10000	300	350364	10100	200	10004	200	10008	1	10000	100
10204	20124	10101	101	10000	100	10000	300	350566	10100	200	10008	200	10004	1	10000	100
10204	20098	10101	101	10000	100	10004	300	349494	10104	200	10012	200	10004	1	10000	100
10204	20120	10101	101	10000	100	10000	300	349720	10100	200	10008	200	10012	1	10000	100
10204	20098	10101	101	10000	100	10000	300	350696	10100	200	10008	200	10012	1	10000	100
10204	20043	10101	101	10000	100	10000	300	350440	10100	200	10008	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0070

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19350	10011	11	10000	10	10000	30	331478	10010	20	10000	20	10006	1	10000	10
10024	20890	10011	11	10000	10	10000	30	362272	10010	20	10000	20	10000	1	10000	10
10024	20786	10011	11	10000	10	10000	30	360070	10010	20	10000	20	10000	1	10000	10
10024	20725	10011	11	10000	10	10000	30	362558	10010	20	10000	20	10000	1	10000	10
10024	20627	10011	11	10000	10	10000	30	349918	10010	20	10000	20	10000	1	10000	10
10024	20089	10011	11	10000	10	10000	30	350036	10010	20	10000	20	10000	1	10000	10
10024	20094	10011	11	10000	10	10000	30	351062	10010	20	10000	20	10000	1	10000	10
10024	20095	10011	11	10000	10	10000	30	350044	10010	20	10000	20	10000	1	10000	10
10024	20070	10011	11	10000	10	10000	30	348004	10010	20	10000	20	10000	1	10000	10
10024	20746	10131	11	10120	10	10000	30	348884	10010	20	10000	20	10000	1	10000	10