Icestorm: CMP (uxtw, 32-bit) measurements

Code:

  cmp w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	538	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	390	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	390	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1, uxtw
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519311	20107	20214	30221	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	0	519496	0	0	20018	20034	0	0	30020	20001	10010
20024	20030	20011	20011	20010	0	519956	0	0	20058	20079	0	0	30044	20001	10010
20024	20030	20011	20011	20010	0	519526	0	0	20019	20034	0	0	30020	20001	10010
20024	20030	20011	20011	20010	4250	297697	99851	158	14661	12630	4959	20	30020	20001	10010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	30020	20001	10010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	30020	20001	10010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	30020	20001	10010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	30020	20001	10010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	30020	20001	10010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1, uxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519434	20107	20214	30224	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29279	80113	80113	80118	240354	80118	80218	160242	80014	100
80205	29102	80154	80154	80158	240357	80119	80220	160240	80015	100
80204	29095	80113	80113	80118	240351	80117	80220	160240	80014	100
80204	29067	80115	80115	80119	240357	80119	80220	160240	80013	100
80204	29092	80113	80113	80118	240357	80119	80220	160240	80013	100
80204	29075	80115	80115	80119	240357	80119	80220	160240	80015	100
80204	29114	80114	80114	80119	240351	80117	80220	160232	80012	100
80204	29004	80113	80113	80118	240357	80119	80220	160240	80015	100
80204	29114	80114	80114	80119	240354	80118	80220	160240	80013	100
80204	29051	80115	80115	80119	240357	80119	80220	160240	80012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30182	80034	80034	80039	240138	80038	80038	160020	80011	10
80024	29100	80021	80021	80020	240101	80020	80020	160020	80011	10
80024	29132	80021	80021	80020	240097	80020	80020	160020	80011	10
80024	28936	80021	80021	80020	240111	80020	80020	160020	80011	10
80024	28974	80021	80021	80020	240081	80020	80020	160020	80011	10
80024	29070	80021	80021	80020	240087	80020	80020	160140	80062	10
80024	29005	80021	80021	80020	240140	80020	80020	160020	80011	10
80024	29058	80021	80021	80020	240106	80020	80020	160020	80011	10
80024	29109	80021	80021	80020	240111	80020	80020	160020	80011	10
80024	28933	80021	80021	80020	240111	80020	80020	160020	80011	10

CMP (uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations