Icestorm: CMP (shifted immediate, 32-bit) measurements

Code:

  cmp w0, #3, lsl #12

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	539	1001	1001	1000	3000	1000	1000	1000	1001
1004	396	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	394	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	394	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmp w0, #3, lsl #12
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519312	20107	20212	20216	20001	10100
20204	20030	20101	20101	20108	519442	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12
  cmp w0, #3, lsl #12

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29333	80115	80115	80119	240354	80118	80220	80220	80013	100
80204	29086	80113	80113	80118	240357	80119	80220	80220	80013	100
80204	29095	80113	80113	80118	240354	80118	80220	80220	80012	100
80204	29035	80115	80115	80119	240357	80119	80220	80220	80015	100
80204	29107	80115	80115	80119	240354	80118	80220	80220	80012	100
80204	29075	80115	80115	80119	240357	80119	80220	80220	80015	100
80204	29092	80113	80113	80118	240354	80118	80220	80220	80013	100
80204	29082	80115	80115	80119	240357	80119	80220	80220	80015	100
80204	29084	80112	80112	80117	240354	80118	80220	80260	80053	100
80204	29072	80112	80112	80117	240354	80118	80220	80220	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3624

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30084	80035	80035	80039	240144	80039	80040	80020	80011	10
80024	28970	80021	80021	80020	240095	80020	80020	80020	80011	10
80024	29201	80021	80021	80020	240087	80020	80020	80020	80011	10
80024	29069	80021	80021	80020	240072	80020	80020	80020	80011	10
80024	28981	80021	80021	80020	240068	80020	80020	80020	80011	10
80024	28932	80021	80021	80020	240088	80020	80020	80020	80011	10
80024	29132	80021	80021	80020	240085	80020	80020	80020	80011	10
80024	29036	80021	80021	80020	240088	80020	80020	80020	80011	10
80024	28977	80021	80021	80020	240068	80020	80020	80020	80011	10
80024	28934	80021	80021	80020	240079	80020	80020	80020	80011	10

CMP (shifted immediate, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations