Icestorm: ADRP measurements

Code:

  .word 0x90000020

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.500

Integer unit issues: 0.501

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	? int output thing (e9)	? int retires (ef)
1004	530	500	500	499	1497	499	1000	500	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000

Count: 8

Code:

  .word 0x90000020
  .word 0x90000021
  .word 0x90000022
  .word 0x90000023
  .word 0x90000024
  .word 0x90000025
  .word 0x90000026
  .word 0x90000027

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	20268	40010	40010	40013	120039	40013	80226	200	39910	80100
80204	20107	40010	40010	40013	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	39909	80100
80204	20086	40009	40009	40012	120135	40047	80295	200	39909	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	21999	40022	40022	40025	120052	40011	80020	20	40001	80010
80024	21469	40022	40022	40025	120094	40025	80050	20	40012	80010
80024	20060	40020	40020	40023	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010

ADRP

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations