Icestorm: ASR (register, 32-bit) measurements

Code:

  asr w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  asr w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259179	10108	10214	20228	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259528	10030	10038	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Code:

  asr w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259434	10107	10214	20228	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20228	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10205	10060	10115	10115	10147	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259528	10030	10038	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010

Test 4: throughput

Count: 8

Code:

  asr w0, w8, w9
  asr w1, w8, w9
  asr w2, w8, w9
  asr w3, w8, w9
  asr w4, w8, w9
  asr w5, w8, w9
  asr w6, w8, w9
  asr w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26867	80115	80115	0	80120	240360	80120	80222	160242	80014	80100
80204	26742	80114	80114	0	80119	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	0	80120	240360	80120	80224	160248	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	27968	80037	80037	80042	264148	80043	80046	160020	80011	80010
80024	26764	80021	80021	80020	277404	80020	80020	160020	80011	80010
80024	26713	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26713	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26713	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26743	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26719	80021	80021	80020	277404	80020	80020	160020	80011	80010
80024	26713	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26713	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26713	80021	80021	80020	282738	80020	80020	160020	80011	80010

ASR (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations