Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLXRH

Test 1: uops

Code:

  stlxrh w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	3154	1019	1	1018	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000

Test 2: throughput

Code:

  stlxrh w0, w1, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0417

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20206	30675	20194	10158	0	10036	10157	0	10003	35479	339385	20106	10203	10003	10203	20006	10004	10000	10100
20204	30435	20104	10104	0	10000	10103	0	10002	35467	339130	20104	10202	10002	10202	20004	10003	10000	10100
20204	30420	20103	10103	0	10000	10102	0	10002	35467	339130	20104	10202	10002	10202	20004	10003	10000	10100
20204	30421	20103	10103	0	10000	10102	0	10002	35467	339339	20104	10202	10002	10202	20004	10003	10000	10100
20204	30433	20103	10103	0	10000	10102	0	10002	35467	339069	20104	10202	10002	10202	20004	10003	10000	10100
20204	30414	20103	10103	0	10000	10102	0	10002	35467	339040	20104	10202	10002	10202	20004	10003	10000	10100
20204	30425	20103	10103	0	10000	10102	0	10002	35467	339037	20104	10202	10002	10202	20004	10003	10000	10100
20204	30421	20103	10103	0	10000	10102	0	10002	35467	339108	20104	10202	10002	10202	20004	10003	10000	10100
20204	30423	20103	10103	0	10000	10102	0	10002	35467	339209	20104	10202	10002	10202	20004	10003	10000	10100
20204	30417	20103	10103	0	10000	10102	0	10002	35467	339156	20104	10202	10002	10202	20004	10003	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0456

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20026	30706	20102	10066	0	10036	10065	0	10002	35242	339907	20014	10022	10002	10020	20000	10001	10000	10010
20024	30467	20011	10011	0	10000	10010	0	10000	35235	339542	20010	10020	10000	10020	20000	10001	10000	10010
20024	30445	20011	10011	0	10000	10010	0	10000	35235	339818	20010	10020	10000	10020	20000	10001	10000	10010
20024	30465	20011	10011	0	10000	10010	0	10000	35235	339416	20010	10020	10000	10020	20000	10001	10000	10010
20024	30448	20011	10011	0	10000	10010	0	10000	35235	339507	20010	10020	10000	10084	20128	10063	10000	10010
20024	30464	20011	10011	0	10000	10010	0	10000	35235	339941	20010	10020	10000	10020	20000	10001	10000	10010
37873	57723	35132	18555	71	16506	18020	73	10000	35235	339931	20010	10020	10000	10022	20004	10003	10000	10010
20024	30462	20014	10014	0	10000	10013	0	10000	35235	339766	20010	10020	10000	10020	20000	10001	10000	10010
20024	30466	20011	10011	0	10000	10010	0	10000	35235	340108	20010	10020	10000	10020	20000	10001	10000	10010
20024	30439	20011	10011	0	10000	10010	0	10000	35235	339715	20010	10020	10000	10020	20000	10001	10000	10010

Test 3: throughput

Code:

  stlxrh w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10205	30150	10119	101	10018	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	30159	10029	11	10018	10	10000	30	528945	10010	20	10000	20	20000	1	10000	10
10024	30049	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30050	10011	11	10000	10	10000	30	528909	10010	20	10000	20	20000	1	10000	10
10024	30049	10011	11	10000	10	10000	30	528999	10010	20	10000	20	20000	1	10000	10
10024	30054	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30117	10011	11	10000	10	10000	30	529089	10010	20	10000	20	20000	1	10000	10
10024	30053	10011	11	10000	10	10036	30	530169	10046	20	10044	20	20000	1	10000	10
10024	30068	10011	11	10000	10	10000	30	528855	10010	20	10004	20	20000	1	10000	10