Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TBZ (not taken)

Test 1: uops

Code:

  tbz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	9942	5892	5892	8100	6504	2168	2227	1009	1
1004	3391	1001	1001	1000	3000	1000	1000	1000	1
1004	2614	1001	1001	1000	3000	1000	1000	1000	1
1004	2551	1001	1001	1000	3000	1000	1000	1000	1
1004	2752	1001	1001	1000	3000	1000	1000	8981	1
1004	4081	1254	1254	1323	3009	1003	1003	1000	1
1004	2815	1001	1001	1000	3000	1000	1000	1000	1
1004	2629	1001	1001	1000	3000	1000	1000	1000	1
1004	2683	1001	1001	1000	3000	1000	1000	1000	1
1004	2737	1001	1001	1000	3000	1000	1000	9378	1

Test 2: throughput

Count: 8

Code:

  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4

Initialization

  mov x0, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5836

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53805	83922	83922	85561	241809	80603	80822	80493	1	100
80204	46787	80169	80169	80197	240372	80124	80228	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80387	1	100
80204	46687	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	121101	119493	119493	136308	250281	83427	84388	82304	1	10
80025	48764	81289	81289	81854	241734	80578	80732	80263	1	10
80024	46791	80077	80077	80104	240171	80057	80077	80044	1	10
80024	46719	80029	80029	80034	240066	80022	80038	80285	1	10
80024	46719	80029	80029	80034	240066	80022	80038	80038	1	10
80024	46709	80019	80019	80022	240066	80022	80032	80038	1	10
80024	46709	80019	80019	80022	240066	80022	80038	80038	1	10
80024	46709	80019	80019	80022	240066	80022	80038	80038	1	10
80024	46709	80019	80019	80022	240066	80022	80038	80038	1	10
80024	46709	80019	80019	80022	240066	80022	80038	80038	1	10