Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
mov w0, #0xaaaaaaaa nop ; nop ; nop
(no loop instructions)
Retires (minus 3 nops): 1.000
Issues: 0.000
Integer unit issues: 0.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | map int uop (7c) | ? int output thing (e9) | ? int retires (ef) |
4004 | 2036 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1058 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1078 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
4004 | 1025 | 1 | 1 | 1000 | 1 | 1000 |
Count: 8
Code:
mov w0, #0xaaaaaaaa mov w1, #0xaaaaaaaa mov w2, #0xaaaaaaaa mov w3, #0xaaaaaaaa mov w4, #0xaaaaaaaa mov w5, #0xaaaaaaaa mov w6, #0xaaaaaaaa mov w7, #0xaaaaaaaa
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2511
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80204 | 20335 | 40012 | 40012 | 40015 | 120039 | 40013 | 80227 | 200 | 39910 | 80100 |
80204 | 20094 | 40010 | 40010 | 40013 | 120036 | 40012 | 80224 | 200 | 39939 | 80100 |
80204 | 20105 | 40010 | 40010 | 40013 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
80204 | 20086 | 40009 | 40009 | 40012 | 120036 | 40012 | 80224 | 200 | 39909 | 80100 |
Result (median cycles for code divided by count): 0.2510
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80024 | 21956 | 40022 | 40022 | 40025 | 120045 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20196 | 40011 | 40011 | 40010 | 120048 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20098 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |
80024 | 20054 | 40011 | 40011 | 40010 | 120049 | 40010 | 80020 | 20 | 40001 | 80010 |