Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSW (literal)

Test 1: uops

Code:

  ldrsw x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	992	1001	1	1000	1000	11507	1000	1000	1	1000
1004	734	1001	1	1000	1000	11081	1000	1000	1	1000
1004	735	1001	1	1000	1000	11426	1000	1000	1	1000
1004	736	1001	1	1000	1000	11309	1000	1000	1	1000
1004	719	1001	1	1000	1000	11342	1000	1000	1	1000
1004	720	1001	1	1000	1000	11189	1000	1000	1	1000
1004	733	1001	1	1000	1000	11115	1000	1000	1	1000
1004	721	1001	1	1000	1000	11297	1000	1000	1	1000
1004	722	1001	1	1000	1000	11381	1000	1000	1	1000
1004	727	1001	1	1000	1000	11396	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5021

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40410	80101	101	80000	100	80010	302	255274	80110	200	80014	200	1	80000	100
80204	40253	80107	101	80006	100	80011	300	642852	80111	200	80015	200	1	80000	100
80204	40171	80101	101	80000	100	80009	300	642857	80109	200	80012	200	1	80000	100
80204	40155	80101	101	80000	100	80009	300	642803	80109	200	80012	200	1	80000	100
80204	40171	80101	101	80000	100	80009	300	642839	80109	200	80012	200	1	80000	100
80204	40155	80101	101	80000	100	80008	300	641870	80108	200	80012	200	1	80000	100
80204	40169	80101	101	80000	100	80009	300	642947	80109	200	80012	200	1	80000	100
80204	40203	80101	101	80000	100	80009	300	642281	80109	200	80012	200	1	80000	100
80204	40203	80101	101	80000	100	80009	300	642371	80109	200	80012	200	1	80000	100
80204	40209	80101	101	80000	100	80009	300	642353	80109	200	80012	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5163

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	43394	80015	11	80004	10	80000	30	380657	80010	20	80000	20	1	80000	10
80024	41368	80011	11	80000	10	80192	30	566215	80202	20	80228	20	1	80000	10
80024	41287	80011	11	80000	10	80000	30	661153	80010	20	80000	20	1	80000	10
80024	41310	80011	11	80000	10	80000	30	661376	80010	20	80000	20	1	80000	10
80024	41295	80011	11	80000	10	80000	30	661977	80010	20	80000	20	1	80000	10
80024	41305	80011	11	80000	10	80000	30	662121	80010	20	80000	20	1	80000	10
80024	41300	80011	11	80000	10	80000	30	662110	80010	20	80000	20	1	80000	10
80024	41310	80011	11	80000	10	80000	30	662209	80010	20	80000	20	1	80000	10
80024	41291	80011	11	80000	10	80000	30	662191	80010	20	80000	20	1	80000	10
80024	41293	80011	11	80000	10	80000	30	662172	80010	20	80000	20	1	80000	10