Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
swpa w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 72006 | 34634 | 2011 | 1 | 2010 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34160 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34133 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34113 | 2001 | 1 | 2000 | 2002 | 11796 | 2002 | 2002 | 4000 | 1 | 2000 |
| 72004 | 34130 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34133 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34254 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34131 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34130 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34130 | 2001 | 1 | 2000 | 2000 | 11786 | 2000 | 2000 | 4000 | 1 | 2000 |
Code:
swpa w0, w1, [x6] add x6, x6, 4
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0012
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30208 | 60705 | 30215 | 10138 | 20077 | 10139 | 20004 | 35252 | 125674 | 30106 | 10202 | 20004 | 10206 | 40025 | 10006 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125724 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125707 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125720 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20014 | 35270 | 125913 | 30120 | 10206 | 20015 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125729 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125702 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125731 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125723 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60012 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 125721 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
Result (median cycles for code): 6.0019
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 30027 | 60373 | 30080 | 10033 | 20047 | 10033 | 20002 | 35069 | 125983 | 30013 | 10021 | 20003 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125962 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30025 | 60026 | 30025 | 10015 | 20010 | 10016 | 20000 | 35066 | 126008 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125960 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60032 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125935 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125980 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125974 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125991 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125977 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20000 | 35066 | 125960 | 30010 | 10020 | 20000 | 10020 | 40000 | 0 | 10001 | 20000 | 0 | 10010 |
Code:
swpa w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 22.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 20205 | 220148 | 20124 | 101 | 20023 | 100 | 20046 | 300 | 2176867 | 20146 | 200 | 20046 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220051 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175519 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20024 | 300 | 2175707 | 20124 | 200 | 20024 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2176416 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175580 | 20104 | 200 | 20004 | 200 | 40008 | 0 | 1 | 20000 | 0 | 100 |
Result (median cycles for code): 22.0044
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20025 | 220144 | 20034 | 11 | 20023 | 10 | 20004 | 30 | 2172801 | 20014 | 20 | 20004 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40048 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40048 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172803 | 20010 | 20 | 20000 | 20 | 40052 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172796 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |