Icestorm: XAFLAG measurements

Code:

  xaflag

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001

Test 2: Latency 1->1

Code:

  xaflag

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10207	254583	10211	10214	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255005	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10

Test 3: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7888

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63319	160114	160114	160120	688162	160118	160218	80211	160012	100
160204	63118	160119	160119	160124	690371	160118	160218	80210	160015	100
160204	63111	160111	160111	160115	689285	160118	160220	80210	160012	100
160204	63155	160115	160115	160120	687735	160118	160220	80208	160010	100
160205	63125	160148	160148	160158	673376	160157	160259	80209	160012	100
160204	63098	160112	160112	160118	691935	160118	160220	80210	160014	100
160204	63127	160115	160115	160120	690012	160118	160220	80210	160012	100
160204	63103	160111	160111	160115	689825	160118	160218	80210	160012	100
160204	63214	160115	160115	160120	688959	160120	160220	80211	160016	100
160204	63085	160114	160114	160118	686797	160118	160220	80208	160011	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7825

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	64444	160023	160023	160030	697932	160030	160042	80020	0	160001	0	0	10
160024	63143	160011	160011	160010	671716	160010	160020	80020	0	160001	0	0	10
160024	62547	160011	160011	160010	672043	160010	160020	80020	0	160001	0	0	10
160024	62551	160011	160011	160010	672043	160010	160020	80020	0	160001	0	0	10
160024	62588	160011	160011	160010	671907	160010	160020	80020	0	160001	0	0	10
160024	62460	160011	160011	160010	671930	160010	160020	80020	0	160001	0	0	10
160025	62625	160059	160059	160064	671989	160010	160020	80020	0	160001	0	0	10
160024	62534	160011	160011	160010	671974	160010	160020	80020	0	160001	0	0	10
160024	62600	160011	160011	160010	673107	160010	160020	80020	0	160001	0	0	10
160024	62533	160011	160011	160010	671504	160010	160020	80020	0	160001	0	0	10

Test 4: throughput

Count: 4

Code:

  fcmp s0, s0
  xaflag
  xaflag
  xaflag
  xaflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5997

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	23999	50105	40102	10003	40109	10003	0	314854	0	40017	50118	40214	0	10004	40214	20008	40003	100
50204	23981	50106	40103	10003	40114	10004	0	315548	0	40017	50116	40212	0	10004	40209	20006	40001	100
50204	24001	50105	40102	10003	40109	10003	0	315434	0	40012	50112	40209	0	10003	40209	20006	40001	100
50204	24013	50104	40101	10003	40112	10004	0	315354	0	40017	50116	40212	0	10004	40212	20008	40002	100
50204	23991	50105	40102	10003	40112	10004	0	315511	0	40018	50116	40212	0	10004	40209	20006	40002	100
50204	23982	50109	40105	10004	40116	10004	0	315684	0	40044	50152	40241	0	10011	40209	20006	40002	100
50204	24004	50106	40103	10003	40112	10004	0	315388	0	40018	50116	40212	0	10004	40209	20006	40003	100
50204	23990	50104	40101	10003	40112	10004	0	314865	0	40012	50112	40209	0	10003	40209	20006	40001	100
50204	23983	50106	40103	10003	40112	10004	0	314936	0	40016	50120	40216	0	10004	40209	20006	40003	100
50204	23993	50103	40101	10002	40109	10003	0	315704	0	40012	50112	40209	0	10003	40209	20006	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5997

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24058	50017	40014	10003	40022	10004	316490	40017	50028	40034	10004	40020	20000	40001	10
50024	24001	50011	40011	10000	40010	10000	315966	40000	50010	40020	10000	40020	20000	40001	10
50024	23991	50011	40011	10000	40010	10000	315065	40000	50010	40020	10000	40020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	315925	40000	50010	40020	10000	40020	20000	40001	10
50024	24002	50011	40011	10000	40010	10000	317033	40028	50048	40051	10007	40020	20000	40001	10
50024	23981	50011	40011	10000	40010	10000	315628	40000	50010	40020	10000	40020	20000	40001	10
50024	24017	50011	40011	10000	40010	10000	316681	40000	50010	40020	10000	40020	20000	40001	10
50024	24015	50011	40011	10000	40010	10000	315457	40000	50010	40020	10000	40020	20000	40001	10
50025	23983	50053	40042	10011	40052	10011	315747	40000	50010	40020	10000	40020	20000	40001	10
50024	23982	50011	40011	10000	40010	10000	316141	40000	50010	40020	10000	40020	20000	40001	10

Test 5: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  xaflag
  xaflag
  xaflag
  xaflag
  xaflag
  xaflag
  xaflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5567

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39036	80103	80103	80114	549618	80114	80214	70209	80005	100
80204	38935	80110	80110	80115	549186	80114	80216	70207	80004	100
80204	38941	80104	80104	80114	546244	80115	80215	70214	80007	100
80204	38959	80104	80104	80111	550642	80114	80216	70214	80007	100
80205	39007	80136	80136	80151	551288	80111	80212	70210	80002	100
80204	38986	80104	80104	80114	549324	80108	80208	70207	80003	100
80204	38980	80103	80103	80111	550481	80111	80212	70214	80004	100
80204	38907	80104	80104	80108	548872	80114	80216	70210	80005	100
80204	38939	80102	80102	80111	548844	80114	80216	70214	80004	100
80204	38969	80103	80103	80114	548885	80114	80216	70207	80003	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5555

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39138	80029	80029	80039	550104	80046	80046	70020	80011	10
80024	38933	80021	80021	80020	546646	80020	80020	70020	80011	10
80024	38844	80021	80021	80020	545914	80020	80020	70020	80011	10
80024	38980	80021	80021	80020	546911	80020	80020	70020	80011	10
80024	38860	80021	80021	80020	546182	80020	80020	70020	80011	10
80024	38938	80021	80021	80020	546355	80077	80078	70020	80011	10
80024	38855	80021	80021	80020	546416	80020	80020	70020	80011	10
80024	38847	80021	80021	80020	545123	80020	80020	70020	80011	10
80024	38904	80021	80021	80020	547214	80020	80020	70020	80011	10
80024	38894	80021	80021	80020	546691	80020	80020	70020	80011	10

XAFLAG

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations