Icestorm: LDR (register, uxtw, 64-bit) measurements

Code:

  ldr x0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	648	1025	1	1024	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8148	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70145	40108	30107	10001	30130	10003	1859533	693921	40106	30210	10004	60220	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60302	20034	30009	10000	30100
40204	70068	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10015	1859926	694178	40150	30247	10017	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859608	694074	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70158	40018	30017	10001	30040	10000	1859604	693654	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859679	694725	40010	30020	10000	60116	20034	30009	10000	30010
40024	70047	40013	30013	10000	30010	10000	1860030	694868	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1861200	695342	40010	30020	10000	60020	20000	30003	10000	30010
40024	70057	40013	30013	10000	30010	10000	1859706	694736	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70148	40108	30107	10001	30130	10003	1859485	693876	40106	30210	10004	60220	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10015	1859737	694110	40150	30251	10017	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70159	40018	30017	10001	30040	10053	1866131	697981	0	40195	30174	10053	0	60020	20000	30002	10000	30010
40024	70107	40013	30013	10000	30010	10000	1859733	694754	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859760	694758	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60172	20052	30020	10000	30010
40024	70054	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	40206	80127	101	80026	100	80008	300	280262	80108	200	80012	200	160028	1	80000	0	100
80204	40060	80101	101	80000	100	80010	300	640424	80110	200	80014	1651	161240	659	80596	3	1030
80204	40064	80101	101	80000	100	80010	300	640352	80110	200	80014	200	160024	1	80000	0	100
80204	40062	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	0	100
80204	40056	80101	101	80000	100	80059	300	634386	80159	200	80072	200	160024	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640304	80108	200	80012	200	160024	1	80000	0	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	0	100
80204	40059	80101	101	80000	100	80008	300	640268	80108	200	80012	202	160138	2	80000	0	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160028	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40272	80037	11	80026	10	80010	30	571304	80020	20	80014	20	160000	1	80000	10
80024	40060	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10

LDR (register, uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations