Icestorm: LDR (pre-index, 32-bit) measurements

Code:

  ldr w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1228	2039	1020	1019	1042	1000	21435	18002	2000	1000	1000	1000	1000	1001	1000	1000
2004	1082	2001	1001	1000	1000	1000	21462	17629	2000	1000	1000	1000	1000	1001	1000	1000
2004	1079	2001	1001	1000	1000	1000	21277	17596	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	20783	17734	2000	1000	1000	1000	1000	1001	1000	1000
2004	1081	2001	1001	1000	1000	1000	20767	17718	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	21473	17630	2000	1000	1000	1000	1000	1001	1000	1000
2004	1084	2001	1001	1000	1000	1000	21171	17628	2000	1000	1000	1000	1000	1001	1000	1000
2004	1077	2001	1001	1000	1000	1000	21496	17611	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	21250	17674	2000	1000	1000	1000	1000	1001	1000	1000
2004	1065	2001	1001	1000	1000	1000	21534	17652	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0120

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71406	50167	40162	10005	40247	10002	1850182	534654	50108	40211	10003	70221	10004	40004	10000	40100
50204	70092	50103	40103	10000	40106	10003	1850118	534698	50109	40212	10004	70221	10004	40004	10000	40100
50204	70106	50104	40104	10000	40106	10003	1852332	535432	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534698	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534698	50109	40212	10004	70289	10013	40015	10000	40100
50204	70092	50103	40103	10000	40106	10003	1850118	534698	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534698	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534698	50109	40212	10004	70221	10004	40004	10000	40100
50204	70110	50104	40104	10000	40106	10003	1850334	534769	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534698	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0099

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71225	50070	40065	10005	40156	10003	1850802	535260	50019	40032	10004	70109	10013	40016	10000	40010
50024	70137	50014	40014	10000	40010	10000	1851227	535382	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850552	535159	50010	40020	10000	70020	10000	40004	10000	40010
50025	70274	50027	40025	10002	40049	10000	1850660	535195	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535177	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535177	50010	40020	10000	70020	10000	40004	10000	40010
50024	70114	50014	40014	10000	40010	10000	1851551	535492	50010	40020	10000	70020	10000	40004	10000	40010
50025	70203	50028	40026	10002	40050	10003	1853642	535952	50019	40032	10004	70020	10000	40009	10000	40010
50024	70178	50019	40019	10000	40010	10000	1852361	535708	50010	40020	10000	70020	10000	40009	10000	40010
50024	70178	50019	40019	10000	40010	10000	1852361	535708	50010	40020	10000	70020	10000	40009	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6, #8]!
  ldr w0, [x7, #8]!
  ldr w0, [x8, #8]!
  ldr w0, [x9, #8]!
  ldr w0, [x10, #8]!
  ldr w0, [x11, #8]!
  ldr w0, [x12, #8]!
  ldr w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44209	160416	80312	80104	80315	80012	240578	642006	160124	80212	80012	80212	80012	80009	80000	80100
160204	43225	160109	80109	80000	80112	80009	240485	642382	160121	80212	80012	80208	80008	80007	80000	80100
160204	43215	160109	80109	80000	80112	80012	240485	644410	160124	80212	80012	80212	80012	80009	80000	80100
160204	43215	160109	80109	80000	80112	80011	240485	642111	160123	80212	80012	80212	80012	80009	80000	80100
160206	43445	160250	80189	80061	80192	80008	240510	641405	160120	80212	80012	80212	80012	80009	80000	80100
160204	43218	160109	80109	80000	80112	80010	240485	642513	160122	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80011	240485	642538	160123	80212	80012	80212	80012	80009	80000	80100
160204	43216	160109	80109	80000	80112	80010	240485	643082	160122	80212	80012	80212	80012	80009	80000	80100
160204	43216	160109	80109	80000	80112	80011	240485	643213	160123	80212	80012	80212	80012	80009	80000	80100
160204	43218	160109	80109	80000	80112	80010	240485	642056	160122	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44319	160319	80221	80098	80224	80013	240311	644232	160036	80033	80013	80032	80012	80009	80000	80010
160024	43221	160011	80011	80000	80010	80000	240179	641620	160010	80020	80000	80020	80000	80001	80000	80010
160024	43214	160011	80011	80000	80010	80000	240179	635542	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	641853	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	646341	160010	80020	80000	80020	80000	80001	80000	80010
160024	43221	160011	80011	80000	80010	80000	240179	641957	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240179	643420	160010	80020	80000	80020	80000	80001	80000	80010
160024	43213	160011	80011	80000	80010	80000	240179	643764	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	633285	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	643108	160010	80020	80000	80020	80000	80001	80000	80010

LDR (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations