Icestorm: MNEG (64-bit) measurements

Code:

  mneg x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  mneg x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	20212	10001	10100
10205	30060	10106	10106	10114	260259	10114	10228	20216	10001	10100
10204	30030	10101	10101	10100	260150	10100	10206	20212	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	0	0	10020	0	259907	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20196	10039	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Code:

  mneg x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260150	10100	10206	20212	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	0	0	10020	0	259907	10020	10020	20084	10016	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	260019	10034	10052	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	0	0	10020	0	259916	10020	10020	20020	10011	10010

Test 4: throughput

Count: 8

Code:

  mneg x0, x8, x9
  mneg x1, x8, x9
  mneg x2, x8, x9
  mneg x3, x8, x9
  mneg x4, x8, x9
  mneg x5, x8, x9
  mneg x6, x8, x9
  mneg x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	80054	80104	80104	80105	0	240315	0	0	80105	80210	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160272	80020	80100
80204	80054	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160472	80108	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160274	80026	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80046	80025	80025	80026	240078	80026	80034	160020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80032	80021	80021	80020	240132	80045	80056	160020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	160020	80011	80010
80025	80067	80041	80041	80045	240060	80020	80020	160020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80032	80021	80021	80020	240132	80045	80058	160020	80011	80010

MNEG (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations