Icestorm: STR (register, uxtw, 32-bit) measurements

Code:

  str w0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1148	1019	1	1018	1000	17079	1000	1000	3000	1	1000
1004	1042	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16955	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16901	1000	1000	3000	1	1000
1004	1040	1001	1	1000	1000	16883	1000	1000	3000	1	1000

Count: 8

Code:

  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	80153	80119	101	80018	100	80001	300	1359938	80101	200	80008	200	240024	1	80000	0	100
80204	80045	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240156	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359958	80101	200	80008	200	240024	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	240024	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	1	80000	0	100
80204	80038	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240147	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80156	80029	11	80018	10	80036	30	1360127	80046	20	80051	20	240024	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80036	30	1360127	80046	20	80051	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360241	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10

STR (register, uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations