Icestorm: SUBS (shifted immediate, 32-bit) measurements

Code:

  subs w0, w0, #3, lsl #12

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Code:

  subs w0, w0, #3, lsl #12

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251647	10109	10210	10210	10001	10100
10204	10030	10101	10101	10108	251819	10107	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10205	10060	10115	10115	10147	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253292	10028	10030	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  subs w0, w1, #3, lsl #12
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20204	20030	20101	20101	20107	519435	20107	20212	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20107	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	0	0	20001	0	0	20100
20205	20060	20117	20117	20150	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20130	20144	20144	20196	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	0	0	20001	0	0	20100
20204	20030	20101	20101	20108	520481	20195	20306	20216	0	0	20001	0	0	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20017	519638	20018	20036	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	20010

Test 4: throughput

Count: 8

Code:

  subs w0, w8, #3, lsl #12
  subs w1, w8, #3, lsl #12
  subs w2, w8, #3, lsl #12
  subs w3, w8, #3, lsl #12
  subs w4, w8, #3, lsl #12
  subs w5, w8, #3, lsl #12
  subs w6, w8, #3, lsl #12
  subs w7, w8, #3, lsl #12

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40114	80110	80110	80113	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	80216	80012	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	40059	80029	80029	80032	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	80011	80010

SUBS (shifted immediate, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations