Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

B

Test 1: uops

Code:

  b .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	? int output thing (e9)
1004	3068	1	1	1
1004	2206	1	1	1
1004	2024	1	1	1
1004	1902	1	1	1
1004	1842	1	1	1
1004	1814	1	1	1
1004	2145	1	1	1
1004	2156	1	1	1
1005	1948	1	1	1
1004	1851	1	1	1

Test 2: throughput

Count: 8

Code:

  b .+4
  b .+4
  b .+4
  b .+4
  b .+4
  b .+4
  b .+4
  b .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0490

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	85200	101	101	100	300	100	200	200	0	1	0	0	100
80205	84427	101	101	100	300	100	200	200	0	1	0	0	100
80204	84002	101	101	100	300	100	200	200	0	1	0	0	100
80204	83894	101	101	100	300	100	200	200	0	1	0	0	100
80204	83927	101	101	100	300	100	200	200	0	1	0	0	100
80204	83836	101	101	100	300	100	200	200	0	1	0	0	100
80204	83921	101	101	100	300	100	200	200	0	1	0	0	100
80204	83939	101	101	100	300	100	200	200	0	1	0	0	100
80204	83457	101	101	100	300	100	200	200	0	1	0	0	100
80204	84008	101	101	100	300	100	200	200	0	1	0	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.9730

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	240383	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80024	238520	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80024	237884	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80025	237966	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80024	237931	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80025	237978	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80025	238171	11	11	0	0	10	0	8955	405427	138730	6735	25032	21088	10470	276	20	0	0	1	0	0	10
80024	237941	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80024	237881	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10
80025	238036	11	11	0	0	10	0	0	30	0	0	10	20	0	0	20	0	0	1	0	0	10