Icestorm: LDR (register, sxtw, 64-bit) measurements

Code:

  ldr x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	656	1027	1	1026	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859539	693896	40106	30210	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60220	20008	30003	10000	30100
40204	70133	40103	30103	10000	30103	10003	1859932	694204	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40205	70079	40111	30109	10002	30135	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70525	40018	30017	10001	30040	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10015	1859827	694441	40060	30067	10017	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70044	40012	30012	10000	30010	10015	1859881	694358	40060	30067	10017	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70291	40108	30107	10001	30130	10003	1859587	693941	40106	30210	10004	60220	20008	30003	10000	30100
40204	70091	40103	30103	10000	30103	10003	1860310	694358	40106	30212	10004	60220	20008	30003	10000	30100
40204	70060	40102	30102	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40205	70072	40110	30108	10002	30135	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859662	694094	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70153	40018	30017	10001	30040	10000	1859922	694821	40010	30020	10000	60020	20000	30002	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10015	1859881	694805	40060	30071	10017	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]
  ldr x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40183	80131	101	80030	100	80008	300	256190	80108	200	80012	200	160028	1	80000	100
80204	40070	80101	101	80000	100	80008	300	640520	80108	200	80012	200	160024	1	80000	100
80204	40058	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160142	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40070	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40369	80041	11	80030	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640220	80010	20	80000	20	160254	1	80000	10
80024	40146	80011	11	80000	10	80010	30	254354	80020	20	80014	20	160000	1	80000	10
80024	40058	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80059	30	640774	80069	20	80071	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640148	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640184	80010	20	80000	20	160000	1	80000	10
80024	40048	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10

LDR (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations