Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (32-bit)

Test 1: uops

Code:

  ldr w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	650	1027	1	1026	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8256	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8328	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8256	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8346	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8292	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8364	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70152	40108	30107	10001	30130	10003	1859587	694038	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1861795	694963	40106	30212	10004	60224	10004	30003	10000	30100
40204	70055	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40026	70192	40026	30023	10003	30072	10003	1859677	694713	40016	30032	10004	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70095	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40179	80125	101	80024	100	80059	300	480640	80159	200	80072	200	80012	1	80000	100
80204	40067	80105	101	80004	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40066	80101	101	80000	100	80008	300	640682	80108	200	80012	200	80012	1	80000	100
80204	40065	80105	101	80004	100	80008	300	276366	80108	200	80012	200	80012	1	80000	100
80204	40064	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40259	80041	11	80030	10	80008	30	400262	80018	20	80012	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40067	80011	11	80000	10	80000	30	640310	80010	20	80000	20	80228	1	80000	10
80024	40078	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40061	80011	11	80000	10	80000	30	640256	80010	20	80000	20	80114	1	80000	10
80024	40092	80011	11	80000	10	80057	30	470231	80067	20	80069	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40055	80011	11	80000	10	80192	30	565606	80202	20	80228	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10