Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (32-bit)

Test 1: uops

Code:

  ldr w0, [x6]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056501027110261000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000825610001000100011000
10045541001110001000832810001000100011000
10045541001110001000825610001000100011000
10045541001110001000834610001000100011000
10045541001110001000829210001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000836410001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570152401083010710001301301000318595876940384010630212100046022410004300031000030100
4020470049401033010310000301031000318617956949634010630212100046022410004300031000030100
4020470055401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002670192400263002310003300721000318596776947134001630032100046002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470095400133001310000300101000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002010000300031000030010

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  ldr w0, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540179801251018002410080059300480640801592008007220080012180000100
8020440067801051018000410080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440066801011018000010080008300640682801082008001220080012180000100
8020440065801051018000410080008300276366801082008001220080012180000100
8020440064801011018000010080008300640268801082008001220080012180000100
8020440056801011018000010080008300640268801082008001220080012180000100
8020440056801011018000010080008300640268801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540259800411180030108000830400262800182080012208000018000010
8002440054800111180000108000030640112800102080000208000018000010
8002440067800111180000108000030640310800102080000208022818000010
8002440078800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440061800111180000108000030640256800102080000208011418000010
8002440092800111180000108005730470231800672080069208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440055800111180000108019230565606802022080228208000018000010
8002440047800111180000108000030640112800102080000208000018000010