Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MRS (FPCR)

Test 1: uops

Code:

  mrs x0, fpcr

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)? int output thing (e9)? int retires (ef)
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000
100412791001100110011000

Test 2: throughput

Count: 8

Code:

  mrs x0, fpcr
  mrs x1, fpcr
  mrs x2, fpcr
  mrs x3, fpcr
  mrs x4, fpcr
  mrs x5, fpcr
  mrs x6, fpcr
  mrs x7, fpcr

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2504

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
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8020410003580101801011003001002002008000180100
8020510006480110801101003001002002008000180100
8020410003580101801011003001002002008000180100
8020410003580101801011003001002002008000180100
8020410003580101801011003001002002008000180100
8020410003580101801011003001002002008000180100
8020410003580101801011003001002002008000180100
8020410003580101801011003001002002008000180100
8020410003580101801011003001002002008000180100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2504

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
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80024100029800118001110301020208000180010
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