Icestorm: LDR (register, lsl, 32-bit) measurements

Code:

  ldr w0, [x6, x7, lsl #2]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	666	1027	1	1026	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8292	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8292	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70147	40108	30107	10001	30130	10003	1859587	693943	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10015	1861735	694924	40150	30251	10017	60224	20010	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60220	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60302	20036	30009	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70197	40018	30017	10001	30040	10000	1859733	694744	40010	30020	10000	60020	20000	30002	10000	30010
40024	70417	40060	30048	10012	30142	10000	1859949	694840	40010	30020	10000	60020	20000	30003	10000	30010
40024	70053	40012	30012	10000	30010	10000	1859706	694741	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859814	694784	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40025	70095	40021	30019	10002	30042	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70145	40108	30107	10001	30130	10003	1859593	693920	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40205	70077	40111	30109	10002	30135	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70170	40018	30017	10001	30040	10000	1860279	693904	40010	30020	10000	60020	20000	0	30004	10000	0	30010
40024	70072	40014	30014	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1861614	695506	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40024	70057	40013	30013	10000	30010	10000	1859733	694744	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40025	70079	40021	30019	10002	30045	10000	1859976	694844	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40025	70081	40021	30019	10002	30045	10000	1859706	694734	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40024	70051	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	0	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	0	30003	10000	0	30010

Test 4: throughput

Count: 8

Code:

  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40172	80129	101	80028	100	80008	300	256100	80108	200	80012	200	160024	1	80000	100
80204	40048	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640214	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640160	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40235	80039	11	80028	10	80008	30	400298	80018	20	80012	20	160028	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40062	80011	11	80000	10	80010	30	543206	80020	20	80014	20	160000	1	80000	10
80024	40055	80011	11	80000	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10
80024	40058	80011	11	80000	10	80000	30	640436	80010	20	80000	20	160000	1	80000	10
80024	40057	80011	11	80000	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10
80024	40052	80011	11	80000	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10
80024	40052	80011	11	80000	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10
80024	40052	80011	11	80000	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10
80024	40052	80011	11	80000	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10

LDR (register, lsl, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations