Icestorm: CMN (uxtx, 64-bit) measurements

Code:

  cmn x0, x1, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	522	1001	1001	1000	3000	1000	1000	2000	1001
1004	394	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	395	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	389	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1, uxtx
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20030	20101	20101	20107	519435	20107	20214	30292	0	20015	0	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	0	20001	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30116	20015	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1, uxtx
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519311	20107	20214	30221	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx
  cmn x0, x1, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29237	80112	80112	80117	240354	80118	80218	160242	80014	100
80204	29112	80114	80114	80119	240351	80117	80220	160240	80013	100
80204	29086	80113	80113	80118	240357	80119	80221	160240	80013	100
80204	29170	80113	80113	80118	240357	80119	80220	160240	80013	100
80204	29059	80115	80115	80119	240354	80118	80220	160240	80012	100
80204	29060	80115	80115	80120	240354	80118	80220	160240	80015	100
80204	29082	80113	80113	80118	240351	80117	80220	160240	80015	100
80204	29160	80115	80115	80119	240357	80119	80220	160240	80013	100
80204	29051	80115	80115	80119	240351	80117	80220	160240	80013	100
80204	29060	80115	80115	80120	240354	80118	80220	160240	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3630

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30238	80035	80035	80039	240155	80042	80046	160020	80011	10
80024	29015	80021	80021	80020	240113	80020	80020	160020	80011	10
80024	29064	80021	80021	80020	240108	80020	80020	160020	80011	10
80024	29098	80021	80021	80020	240289	80081	80082	160020	80011	10
80024	28906	80021	80021	80020	240103	80020	80020	160020	80011	10
80024	28980	80021	80021	80020	240108	80020	80020	160020	80011	10
80024	29070	80021	80021	80020	240096	80020	80020	160020	80011	10
80024	29059	80021	80021	80020	240116	80020	80020	160020	80011	10
80024	29112	80021	80021	80020	240097	80020	80020	160020	80011	10
80024	28933	80021	80021	80020	240113	80020	80020	160020	80011	10

CMN (uxtx, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations