Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (64-bit)

Test 1: uops

Code:

  str x0, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1005115310191101810001707910001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104910011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000

Test 2: throughput

Count: 8

Code:

  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0017

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802058025780137101800361008000130013599388010120080008200160016180000100
802048014180119101800181008000130013598508010120080008200160016180000100
802048068580211103801081028010930013633788020920080131200160016180000100
802048003780101101800001008007530013620178017520080092200160102180000100
802048003780101101800001008000130013598508010120080008200160104180000100
802048003780101101800001008003730013599728013720080052200160016180000100
802048036580155101800541008000130013598508010120080008200160016180000100
802048022980137101800361008003930013610818013920080051200160016180000100
802048003780101101800001008018130813658898028320280211200160016180000100
802048022980137101800361008000130013598508010120080008200160510180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258038980047118003610800753013621778008520800922016000018000010
800248004780011118000010800003013600438001020800002016000018000010
800248004780011118000010800003013600438001020800002016032818000010
800248025180047118003610800003013600438001020800002016016418000010
800248004780011118000010800003013600438001020800002016000018000010
800248004780011118000010800003013600438001020800002016016418000010
800248025180047118003610800003013600438001020800002016016418000010
800248004780011118000010800003013600438001020800002016000018000010
800248004780011118000010800003013600438001020800002016000018000010
800248004780011118000010800003013600438001020800002016000018000010