Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
caspal w0, w1, w2, w3, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 6.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 76012 | 34760 | 3022 | 1 | 3021 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34427 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34386 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34393 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34389 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34388 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34388 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2002 | 7007 | 1 | 3000 | 3000 |
| 76004 | 34652 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34387 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34383 | 3001 | 1 | 3000 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
Code:
caspal w0, w1, w2, w3, [x6] add x6, x6, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 19.0050
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 70222 | 191021 | 51194 | 21099 | 0 | 30095 | 21050 | 0 | 30036 | 68030 | 734716 | 52623 | 30235 | 40048 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190050 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68679 | 734570 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190050 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68679 | 734570 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190050 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68679 | 734570 | 52830 | 30202 | 40004 | 30235 | 70084 | 0 | 21394 | 30000 | 0 | 40100 |
| 70204 | 190050 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68679 | 734570 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190050 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68679 | 734570 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190050 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68679 | 734570 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190046 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30003 | 68665 | 734554 | 52830 | 30202 | 40004 | 30235 | 70084 | 0 | 22366 | 30000 | 0 | 40100 |
| 65582 | 174540 | 48838 | 21665 | 0 | 27173 | 21380 | 0 | 30003 | 69048 | 735009 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22732 | 30000 | 0 | 40100 |
| 70204 | 190107 | 52833 | 22832 | 0 | 30001 | 22827 | 0 | 30102 | 69082 | 736030 | 52991 | 30301 | 40136 | 30235 | 70084 | 0 | 22757 | 30000 | 0 | 40100 |
Result (median cycles for code): 19.0050
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 70039 | 190578 | 51053 | 20991 | 0 | 30062 | 20938 | 0 | 30003 | 68482 | 734675 | 0 | 52740 | 30022 | 40004 | 0 | 30055 | 70084 | 0 | 22425 | 30000 | 0 | 40010 |
| 70024 | 190056 | 52747 | 22746 | 0 | 30001 | 22737 | 0 | 30003 | 68416 | 734575 | 0 | 52740 | 30022 | 40004 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70024 | 190050 | 52742 | 22742 | 0 | 30000 | 22737 | 0 | 30000 | 68418 | 734555 | 0 | 52737 | 30020 | 40000 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70024 | 190050 | 52742 | 22742 | 0 | 30000 | 22737 | 0 | 30000 | 68416 | 734581 | 0 | 52737 | 30020 | 40000 | 0 | 53951 | 88856 | 38 | 30695 | 38979 | 88 | 51566 |
| 70024 | 190055 | 52745 | 22744 | 0 | 30001 | 22737 | 0 | 30000 | 68400 | 734535 | 0 | 52737 | 30020 | 40000 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70024 | 190049 | 52742 | 22742 | 0 | 30000 | 22737 | 0 | 30000 | 68400 | 734552 | 0 | 52737 | 30020 | 40000 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70025 | 190123 | 52132 | 22102 | 0 | 30030 | 22097 | 0 | 30000 | 68444 | 734623 | 0 | 52737 | 30020 | 40000 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70024 | 190049 | 52742 | 22742 | 0 | 30000 | 22737 | 0 | 30000 | 68400 | 734552 | 0 | 52737 | 30020 | 40000 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70024 | 190049 | 52742 | 22742 | 0 | 30000 | 22737 | 0 | 30000 | 68400 | 734552 | 0 | 52737 | 30020 | 40000 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
| 70024 | 190049 | 52742 | 22742 | 0 | 30000 | 22737 | 0 | 30036 | 63667 | 734811 | 0 | 51170 | 30055 | 40048 | 0 | 30020 | 70000 | 0 | 22732 | 30000 | 0 | 40010 |
Code:
caspal w0, w1, w2, w3, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 30.0043
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 60209 | 300146 | 51997 | 21959 | 30038 | 11032 | 30024 | 3498592 | 3340438 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 0 | 25460 | 30000 | 0 | 30102 |
| 60207 | 300144 | 54510 | 24464 | 30046 | 12302 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20264 | 70217 | 0 | 23841 | 30000 | 0 | 30104 |
| 60206 | 300043 | 55577 | 25560 | 30017 | 12838 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20238 | 70133 | 0 | 23208 | 30000 | 0 | 30102 |
| 60206 | 300045 | 55577 | 25560 | 30017 | 12838 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20238 | 70133 | 0 | 24532 | 30000 | 0 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 30017 | 12838 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 0 | 25460 | 30000 | 0 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 30017 | 12838 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20238 | 70133 | 0 | 25354 | 30000 | 0 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 30017 | 12838 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 0 | 25460 | 30000 | 0 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 30017 | 12838 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 0 | 25460 | 30000 | 0 | 30102 |
| 60207 | 300121 | 52540 | 22494 | 30046 | 11320 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 0 | 25460 | 30000 | 0 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 30017 | 12838 | 30057 | 3251854 | 3341587 | 0 | 42007 | 20238 | 40076 | 0 | 20216 | 70056 | 0 | 25460 | 30000 | 0 | 30102 |
Result (median cycles for code): 30.0043
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 60029 | 300146 | 51905 | 21867 | 0 | 30038 | 10942 | 0 | 30024 | 3498071 | 3343244 | 42771 | 20036 | 40032 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20058 | 70133 | 21871 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60026 | 300041 | 55482 | 25466 | 0 | 30016 | 12747 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20034 | 70049 | 25456 | 30000 | 30012 |
| 60027 | 300071 | 52690 | 22644 | 0 | 30046 | 11348 | 0 | 30021 | 3498095 | 3343250 | 42768 | 20034 | 40028 | 20058 | 70133 | 23600 | 30000 | 30012 |