Icestorm: LDURSW measurements

Code:

  ldursw x0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	651	1027	1	1026	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8130	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	549	1001	1	1000	1000	8166	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursw x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40206	70265	40116	30113	10003	30162	10003	1859485	693973	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70052	40103	30103	10000	30103	10003	1859851	694170	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60294	10017	30009	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70519	40018	30017	10001	30040	10003	1859920	694803	0	40016	30032	10004	0	60020	10000	30003	10000	30010
40024	70058	40013	30013	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60098	10013	30009	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10000	1859949	694824	0	40010	30020	10000	0	60020	10000	30003	10000	30010
40024	70051	40012	30012	10000	30010	10015	1860313	694965	0	40060	30071	10017	0	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40179	80129	101	80028	100	80008	300	256190	80108	200	80012	200	80012	1	80000	100
80204	40058	80105	101	80004	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80205	40208	80131	101	80030	100	80008	300	320916	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80059	300	620726	80159	200	80072	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40387	80045	11	80034	10	80008	30	640142	80018	20	80012	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40172	80011	11	80000	10	80000	30	640454	80010	20	80000	20	80000	1	80000	10
80024	40053	80011	11	80000	10	80000	30	640274	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80025	40102	80048	11	80037	10	80000	30	360112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10

LDURSW

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations