Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MUL (64-bit)

Test 1: uops

Code:

  mul x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000

Test 2: Latency 1->2

Code:

  mul x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601501010010206202121000110100
10204300301010110101101002601561010010208202121000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1002430030100211002110020025990700100201003000200201001110010
1002430030100211002110020025991600100201002000200201001110010
1002430030100211002110020025991600100201002000200201001110010
1002430030100211002110020025991600100201002000200201001110010
1002430030100211002110020025991600100201002000200361001110010
1002430030100211002110020025991600100201002000200201001110010
1002430030100211002110020025991600100201002000200201001110010
100253006010026100261003457284112685126514022646324101669850200401001110010
1002430030100211002110020025991600100201002000200201001110010
1002430030100211002110020025991600100201002000200201001110010

Test 3: Latency 1->3

Code:

  mul x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601501010010206202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202621000610100
10204300301010110101101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010030200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 4: throughput

Count: 8

Code:

  mul x0, x8, x9
  mul x1, x8, x9
  mul x2, x8, x9
  mul x3, x8, x9
  mul x4, x8, x9
  mul x5, x8, x9
  mul x6, x8, x9
  mul x7, x8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80205800868012080120801240240315008010580210001602208000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80205800668012080120801240240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800248003580025800258002624006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024013280045800561600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010