Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NOP

Test 1: uops

Code:

nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	? int output thing (e9)
1004	545	1	1	1
1004	284	1	1	1
1004	275	1	1	1
1004	275	1	1	1
1004	275	1	1	1
1004	275	1	1	1
1004	275	1	1	1
1004	275	1	1	1
1004	275	1	1	1
1004	275	1	1	1

Test 2: throughput

Count: 8

Code:

  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	20298	101	101	100	300	100	200	200	1	100
80204	20097	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100
80204	20085	101	101	100	300	100	200	200	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	21933	21	21	20	69	20	20	20	11	10
80024	20149	21	21	20	65	20	20	20	11	10
80024	20058	21	21	20	65	20	20	20	11	10
80024	20058	21	21	20	65	20	20	20	11	10
80024	20069	21	21	20	65	20	20	20	11	10
80024	20058	21	21	20	65	20	20	20	11	10
80024	20104	21	21	20	65	20	20	20	11	10
80024	20069	21	21	20	70	20	20	20	11	10
80024	20054	21	21	20	65	20	20	20	11	10
80024	20074	21	21	20	65	20	20	20	11	10