Icestorm: LDURSB (32-bit) measurements

Code:

  ldursb w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	655	1027	1	1026	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursb w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40205	70146	40108	30107	10001	30130	10003	1859485	693973	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40205	70098	40111	30109	10002	30135	10003	1859695	694084	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	0	30003	10000	0	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70306	40018	30017	10001	30040	10015	1860475	694451	40060	30067	10017	60020	10000	30003	10000	30010
40024	70048	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40025	70115	40020	30018	10002	30042	10000	1859787	694769	40010	30020	10000	60020	10000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60044	10004	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859760	694756	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	40199	80131	101	80030	100	80008	300	280262	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640016	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640592	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	0	100
80204	40074	80101	101	80000	100	80008	300	640502	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40168	80033	11	80022	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640544	80010	20	80000	20	80000	1	80000	10

LDURSB (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations