Icestorm: LDRSB (register, uxtw, 64-bit) measurements

Code:

  ldrsb x0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	689	1027	1	1026	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	556	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	556	1001	1	1000	1000	8166	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70511	40108	30107	10001	30130	10003	1859533	693921	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60220	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10015	1861568	694964	40152	30251	10017	60220	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40205	70158	40111	30109	10002	30135	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70161	40018	30017	10001	30040	10003	1859536	694688	40016	30032	10004	60044	20008	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40025	70072	40020	30018	10002	30045	10000	1860306	693945	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70145	40013	30013	10000	30010	10000	1859544	694675	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859652	694719	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	0	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60122	20034	0	30008	10000	0	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859485	693876	40106	30210	10004	60220	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1861336	694776	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1862092	695085	40106	30212	10004	60224	20008	30003	10000	30100
40204	70058	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70155	40018	30017	10001	30040	10003	1859704	693727	40016	30030	10004	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70062	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60122	20036	30009	10000	30010
40024	70053	40013	30013	10000	30010	10729	1888698	705108	41851	31585	10840	60020	20000	30003	10000	30010
40024	70050	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10015	1862122	716891	40060	30068	10017	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	40178	80133	101	80032	100	80008	300	248262	80108	200	80012	200	160028	0	1	80000	0	100
80204	40063	80105	101	80004	100	80008	300	472262	80108	200	80012	200	160144	0	1	80000	0	100
80204	40129	80101	101	80000	100	80008	300	640484	80108	200	80012	200	160024	0	1	80000	0	100
80204	40061	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	0	1	80000	0	100
80204	40059	80101	101	80000	100	80008	300	640376	80108	200	80012	200	160024	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	0	1	80000	0	100
80205	40110	80138	101	80037	100	80008	300	640268	80108	200	80012	200	160024	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	0	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40240	80035	11	80024	10	80008	30	400064	80018	20	80012	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160142	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10

LDRSB (register, uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations