Icestorm: LDRSB (pre-index, 32-bit) measurements

Code:

  ldrsb w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1231	2031	1018	1013	1036	1000	20572	17709	2000	1000	1000	1000	1000	1001	1000	1000
2004	1076	2001	1001	1000	1000	1000	20474	18123	2000	1000	1000	1000	1000	1001	1000	1000
2004	1068	2001	1001	1000	1000	1000	21172	17909	2000	1000	1000	1000	1000	1001	1000	1000
2004	1082	2001	1001	1000	1000	1000	21126	17355	2000	1000	1000	1000	1000	1001	1000	1000
2004	1087	2001	1001	1000	1000	1000	20582	18046	2000	1000	1000	1000	1000	1001	1000	1000
2004	1083	2001	1001	1000	1000	1000	21212	17605	2000	1000	1000	1000	1000	1001	1000	1000
2004	1080	2001	1001	1000	1000	1000	21486	17676	2000	1000	1000	1000	1000	1001	1000	1000
2004	1080	2001	1001	1000	1000	1000	21381	17701	2000	1000	1000	1000	1000	1001	1000	1000
2004	1076	2001	1001	1000	1000	1000	21063	17974	2000	1000	1000	1000	1000	1001	1000	1000
2004	1103	2001	1001	1000	1000	1000	21318	17585	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0121

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71430	50167	40162	10005	40247	10003	1850560	534788	50109	40212	10004	70221	10004	40004	10000	40100
50205	70208	50117	40115	10002	40140	10003	1850636	534844	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534882	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534882	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534882	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534882	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534882	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534882	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10012	1854236	535956	50152	40251	10013	70293	10014	40016	10000	40100
50205	70287	50118	40116	10002	40140	10003	1850712	534900	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0117

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71386	50070	40065	10005	40156	10003	1850883	535283	50019	40032	10004	70020	10000	40004	10000	40010
50024	70110	50014	40014	10000	40010	10000	1850336	535083	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850633	535182	50010	40020	10000	70020	10000	40004	10000	40010
50024	70119	50014	40014	10000	40010	10000	1850552	535155	50010	40020	10000	70020	10000	40004	10000	40010
50025	70187	50027	40025	10002	40048	10000	1850760	535223	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1851011	535308	50010	40020	10000	70113	10014	40018	10000	40010
50024	70275	50029	40026	10003	40046	10010	1852997	536133	50056	40060	10010	70020	10000	40004	10000	40010
50024	70116	50014	40014	10000	40010	10000	1850633	535182	50010	40020	10000	70020	10000	40004	10000	40010
50024	70109	50014	40014	10000	40010	10000	1850471	535128	50010	40020	10000	70020	10000	40004	10000	40010
50024	70104	50014	40014	10000	40010	10000	1850579	535162	50010	40020	10000	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6, #8]!
  ldrsb w0, [x7, #8]!
  ldrsb w0, [x8, #8]!
  ldrsb w0, [x9, #8]!
  ldrsb w0, [x10, #8]!
  ldrsb w0, [x11, #8]!
  ldrsb w0, [x12, #8]!
  ldrsb w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44426	160427	80313	80114	80316	80010	240610	647360	160122	80212	80012	80212	80012	80009	80000	80100
160204	43236	160109	80109	80000	80112	80011	240529	644842	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80012	240529	643503	160124	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80012	240529	643448	160124	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80011	240529	644524	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80011	240529	645965	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80011	240529	645976	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80011	240529	642241	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80012	240529	639355	160124	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80011	240529	641944	160123	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5409

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44376	160340	80222	80118	80225	80009	240340	642592	160031	80032	80012	80020	80000	80001	80000	80010
160025	43318	160082	80052	80030	80051	80000	240304	644225	160010	80020	80000	80032	80012	80009	80000	80010
160024	43276	160011	80011	80000	80010	80000	240707	644984	160010	80020	80000	80020	80000	80001	80000	80010
160024	43272	160011	80011	80000	80010	80000	240707	640692	160010	80020	80000	80020	80000	80001	80000	80010
160024	43272	160011	80011	80000	80010	80000	240704	643047	160010	80020	80000	80020	80000	80001	80000	80010
160024	43270	160011	80011	80000	80010	80000	240704	646085	160010	80020	80000	80020	80000	80001	80000	80010
160024	43272	160011	80011	80000	80010	80000	240702	645723	160010	80020	80000	80020	80000	80001	80000	80010
160024	43272	160011	80011	80000	80010	80000	240707	641911	160010	80020	80000	80020	80000	80001	80000	80010
160024	43272	160011	80011	80000	80010	80000	240702	645188	160010	80020	80000	80020	80000	80001	80000	80010
160024	43272	160011	80011	80000	80010	80000	240704	646010	160010	80020	80000	80020	80000	80001	80000	80010

LDRSB (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations