Icestorm: LDRSH (register, 32-bit) measurements

Code:

  ldrsh w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	676	1021	1	1020	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70153	40108	30107	10001	30130	10003	1859437	693831	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10015	1859737	694074	40150	30247	10017	60220	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70155	40018	30017	10001	30040	10003	1859677	693716	40016	30030	10004	60040	20008	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1861245	695368	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70047	40012	30012	10000	30010	10000	1859868	694807	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40206	70176	40117	30114	10003	30164	10003	1860310	694367	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70146	40018	30017	10001	30040	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859490	694655	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60114	20034	30008	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40025	70157	40021	30019	10002	30045	10000	1859679	694732	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40186	80135	101	80034	100	80008	300	242886	80108	200	80012	200	160028	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80057	300	594324	80157	200	80069	200	160024	1	80000	100
80204	40062	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40267	80101	101	80000	100	80010	300	640280	80110	200	80014	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40304	80035	11	80024	10	80000	30	320166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640310	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80048	30	634053	80058	20	80057	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640076	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10

LDRSH (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations