Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stxr w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 71005 | 35665 | 1003 | 1 | 1002 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34394 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34266 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34391 | 1001 | 1 | 1000 | 1001 | 4007 | 1001 | 1001 | 2000 | 1 | 1000 |
| 71004 | 36077 | 1001 | 1 | 1000 | 1000 | 4003 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33972 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33953 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34266 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33926 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33961 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
stxr w0, w1, [x6] add x6, x6, 4
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.1857
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20207 | 22248 | 20247 | 10193 | 10054 | 10196 | 10005 | 35497 | 233445 | 20110 | 10205 | 10005 | 10205 | 20010 | 10004 | 10000 | 10100 |
| 20204 | 21911 | 20104 | 10104 | 10000 | 10105 | 10004 | 35497 | 232347 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21857 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232474 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21854 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232542 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21861 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232613 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21856 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232575 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21857 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232742 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21866 | 20103 | 10103 | 10000 | 10104 | 10034 | 35833 | 233304 | 20168 | 10234 | 10034 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21857 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232593 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21860 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 232486 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
Result (median cycles for code): 2.1966
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20027 | 22313 | 20152 | 10098 | 10054 | 10103 | 10004 | 35248 | 233907 | 0 | 20018 | 10024 | 10004 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21963 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 233626 | 0 | 20010 | 10020 | 10000 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21961 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 232816 | 0 | 20010 | 10020 | 10000 | 0 | 10023 | 20008 | 10004 | 10000 | 10010 |
| 20024 | 21912 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 233483 | 0 | 20010 | 10020 | 10000 | 0 | 10051 | 20060 | 10032 | 10000 | 10010 |
| 20024 | 21963 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 234390 | 0 | 20010 | 10020 | 10000 | 0 | 10111 | 20180 | 10092 | 10000 | 10010 |
| 20024 | 21995 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 233289 | 0 | 20010 | 10020 | 10000 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21845 | 20011 | 10011 | 10000 | 10010 | 10030 | 35566 | 234281 | 0 | 20071 | 10051 | 10030 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 22017 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 234543 | 0 | 20010 | 10020 | 10000 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 22024 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 234542 | 0 | 20010 | 10020 | 10000 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 22025 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 234546 | 0 | 20010 | 10020 | 10000 | 0 | 10020 | 20000 | 10001 | 10000 | 10010 |
Code:
stxr w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0040
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10205 | 20154 | 10119 | 101 | 10018 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0040
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10025 | 20522 | 10029 | 11 | 10018 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10004 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30251 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 529251 | 10010 | 20 | 10000 | 20 | 20008 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30040 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |